/*
* Start Transmit at the PCU engine (unpause receive)
*/
void
ar5212StartPcuReceive(struct ath_hal *ah)
{
struct ath_hal_private *ahp = AH_PRIVATE(ah);
OS_REG_WRITE(ah, AR_DIAG_SW,
OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
ar5212EnableMibCounters(ah);
/* NB: restore current settings */
ar5212AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
}
/*
* Start receive at the PCU engine
*/
void
ar5416StartPcuReceive(struct ath_hal *ah)
{
struct ath_hal_private *ahp = AH_PRIVATE(ah);
HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__);
ar5212EnableMibCounters(ah);
/* NB: restore current settings */
ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
/*
* NB: must do after enabling phy errors to avoid rx
* frames w/ corrupted descriptor status.
*/
OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
}
static void
enableAniMIBCounters(struct ath_hal *ah, const struct ar5212AniParams *params)
{
struct ath_hal_5212 *ahp = AH5212(ah);
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Enable mib counters: "
"OfdmPhyErrBase 0x%x cckPhyErrBase 0x%x\n",
__func__, params->ofdmPhyErrBase, params->cckPhyErrBase);
OS_REG_WRITE(ah, AR_FILTOFDM, 0);
OS_REG_WRITE(ah, AR_FILTCCK, 0);
OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);
OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);
OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save+clear counters*/
ar5212EnableMibCounters(ah); /* enable everything */
}
