void ar7240_i2sound_i2slink_on(int master) { ar7240_reg_wr(AR7240_STEREO_CONFIG, (AR7240_STEREO_CONFIG_SPDIF_ENABLE| AR7240_STEREO_CONFIG_ENABLE| AR7240_STEREO_CONFIG_RESET| AR7240_STEREO_CONFIG_PCM_SWAP| AR7240_STEREO_CONFIG_MIC_WORD_SIZE| AR7240_STEREO_CONFIG_MODE(0)| AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_16B)| AR7240_STEREO_CONFIG_I2S_32B_WORD| AR7240_STEREO_CONFIG_SAMPLE_CNT_CLEAR_TYPE| AR7240_STEREO_CONFIG_MASTER| AR7240_STEREO_CONFIG_PSEDGE(2) ));//gl-inet //ar7240_reg_wr(AR7240_STEREO_CLK_DIV,0xec330);//gl-inet //ar7240_reg_wr(AR7240_STEREO_CLK_DIV,0xd9013);//gl-inet //ar7240_reg_wr(AR7240_STEREO_CLK_DIV,((0x10 << 16) + 0x4600));//gl-inet 48000kHz ar7240_reg_wr(AR7240_STEREO_CLK_DIV,((0x11 << 16) + 0xb6b0));//gl-inet 44100kHz //init_wm8978(); udelay(100); ar7240_reg_rmw_clear(AR7240_STEREO_CONFIG, AR7240_STEREO_CONFIG_RESET); }
void ar7240_gpio_config_int(int gpio, ar7240_gpio_int_type_t type, ar7240_gpio_int_pol_t polarity) { u32 val; /* * allow edge sensitive/rising edge too */ if (type == INT_TYPE_LEVEL) { /* level sensitive */ ar7240_reg_rmw_set(AR7240_GPIO_INT_TYPE, (1 << gpio)); } else { /* edge triggered */ val = ar7240_reg_rd(AR7240_GPIO_INT_TYPE); val &= ~(1 << gpio); ar7240_reg_wr(AR7240_GPIO_INT_TYPE, val); } if (polarity == INT_POL_ACTIVE_HIGH) { ar7240_reg_rmw_set (AR7240_GPIO_INT_POLARITY, (1 << gpio)); } else { val = ar7240_reg_rd(AR7240_GPIO_INT_POLARITY); val &= ~(1 << gpio); ar7240_reg_wr(AR7240_GPIO_INT_POLARITY, val); } ar7240_reg_rmw_set(AR7240_GPIO_INT_ENABLE, (1 << gpio)); }
void init_s3c2410_iis_bus(void) { ///unsigned long a,b; ar7240_reg_wr(AR7240_STEREO_CONFIG,0); ar7240_reg_wr(AR7240_STEREO_CLK_DIV,0); stereo_config_variable = 0; stereo_config_variable = AR7240_STEREO_CONFIG_SPDIF_ENABLE; stereo_config_variable = stereo_config_variable | AR7240_STEREO_CONFIG_ENABLE; stereo_config_variable = stereo_config_variable | AR7240_STEREO_CONFIG_RESET; stereo_config_variable = stereo_config_variable | AR7240_STEREO_CONFIG_MIC_WORD_SIZE; stereo_config_variable = stereo_config_variable | AR7240_STEREO_CONFIG_MODE(0); stereo_config_variable = stereo_config_variable | AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_16B); stereo_config_variable = stereo_config_variable | AR7240_STEREO_CONFIG_SAMPLE_CNT_CLEAR_TYPE; stereo_config_variable = stereo_config_variable | AR7240_STEREO_CONFIG_MASTER; stereo_config_variable = stereo_config_variable | AR7240_STEREO_CONFIG_PSEDGE(2); ar7240_reg_wr(AR7240_STEREO_CONFIG,0); ar7240_reg_wr(AR7240_STEREO_CONFIG,stereo_config_variable); ar7240_reg_wr(AR7240_STEREO_CLK_DIV,((0x11 << 16) + 0xb6b0)); audio_rate = 44100; udelay(100); ar7240_reg_rmw_clear(AR7240_STEREO_CONFIG, AR7240_STEREO_CONFIG_RESET); }
void ar7240_gpio_config() { /* Disable clock obs */ ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e0ff)); /* Enable eth Switch LEDs */ ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | 0xf8)); }
void ar7240_i2sound_dma_pause(int mode) { //Pause if (mode) { ar7240_reg_wr(MBOX0_DMA_TX_CONTROL, PAUSE); } else { ar7240_reg_wr(MBOX0_DMA_RX_CONTROL, PAUSE); } }
void ar7240_i2sound_dma_start(int mode) { // Start if (mode) { ar7240_reg_wr(MBOX0_DMA_TX_CONTROL, START); } else { ar7240_reg_wr(MBOX0_DMA_RX_CONTROL, START); } }
int serial_init(void) { u32 rdata; u32 baudRateDivisor, clock_step; u32 fcEnable = 0; u32 ahb_freq, ddr_freq, cpu_freq; ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq); /* GPIO Configuration */ ar7240_reg_wr(AR7240_GPIO_OE, 0xcff); rdata = ar7240_reg_rd(AR7240_GPIO_OUT); rdata |= 0x400; // GPIO 10 (UART_SOUT) must output 1 ar7240_reg_wr(AR7240_GPIO_OUT, rdata); rdata = ar7240_reg_rd(AR7240_GPIO_FUNC); /* GPIO_FUN, bit1/UART_EN, bit2/UART_RTS_CTS_EN, bit15(disable_s26_uart) */ rdata |= (0x3 << 1) | (0x1 << 15); ar7240_reg_wr(AR7240_GPIO_FUNC, rdata); /* Get reference clock rate, then set baud rate to 115200 */ // TODO: check the following code rdata = ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS); rdata &= HORNET_BOOTSTRAP_SEL_25M_40M_MASK; if (rdata) { baudRateDivisor = (40000000 / (16 * 115200)) - 1; // 40 MHz clock is taken as UART clock } else { baudRateDivisor = (25000000 / (16 * 115200)) - 1; // 25 MHz clock is taken as UART clock } clock_step = 8192; rdata = UARTCLOCK_UARTCLOCKSCALE_SET(baudRateDivisor) | UARTCLOCK_UARTCLOCKSTEP_SET(clock_step); uart_reg_write(UARTCLOCK_ADDRESS, rdata); /* Config Uart Controller */ /* No interrupt */ rdata = UARTCS_UARTDMAEN_SET(0) | UARTCS_UARTHOSTINTEN_SET(0) | UARTCS_UARTHOSTINT_SET(0) | UARTCS_UARTSERIATXREADY_SET(0) | UARTCS_UARTTXREADYORIDE_SET(~fcEnable) | UARTCS_UARTRXREADYORIDE_SET(~fcEnable) | UARTCS_UARTHOSTINTEN_SET(0); /* is_dte == 1 */ rdata = rdata | UARTCS_UARTINTERFACEMODE_SET(2); if (fcEnable) { rdata = rdata | UARTCS_UARTFLOWCONTROLMODE_SET(2); } /* invert_fc ==0 (Inverted Flow Control) */ //rdata = rdata | UARTCS_UARTFLOWCONTROLMODE_SET(3); /* parityEnable == 0 */ //rdata = rdata | UARTCS_UARTPARITYMODE_SET(2); -->Parity Odd //rdata = rdata | UARTCS_UARTPARITYMODE_SET(3); -->Parity Even uart_reg_write(UARTCS_ADDRESS, rdata); return 0; }
void board_gpiolib_defaults(void) { //set output enable ar7240_reg_wr (AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | (1<<13)|(1<<14)|(1<<0) )); //set ETH0 ETH1 LED output to high ar7240_reg_wr (AR7240_GPIO_SET, (1<<13)|(1<<14)); //set WLAN LED output to low (reverse polarity LED) ar7240_reg_wr (AR7240_GPIO_CLEAR, (1<<0)); //Enable USB boot sense GPIO as input ar7240_reg_wr (AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) & ~(1<<11))); }
void ar7240_i2sound_dma_resume(int mode) { /*MBOX_STATUS * Resume */ if (mode) { ar7240_reg_wr(MBOX0_DMA_TX_CONTROL, RESUME); } else { ar7240_reg_wr(MBOX0_DMA_RX_CONTROL, RESUME); } }
void ar7240_gpio_config() { /* Disable clock obs */ ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e0ff)); /* Enable eth Switch LEDs */ #ifdef CONFIG_K31 ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | 0xd8)); #else ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | 0xfa)); #endif }
void ar7240_i2sound_dma_desc(unsigned long desc_buf_p, int mode) { /* * Program the device to generate interrupts * RX_DMA_COMPLETE for mbox 0 */ if (mode) { ar7240_reg_wr(MBOX0_DMA_TX_DESCRIPTOR_BASE, desc_buf_p); } else { ar7240_reg_wr(MBOX0_DMA_RX_DESCRIPTOR_BASE, desc_buf_p); } }
int ar7240_mem_config(void) { ar7240_ddr_initial_config(CFG_DDR_REFRESH_VAL); ar7240_reg_wr (AR7240_DDR_TAP_CONTROL0, 0x8); ar7240_reg_wr (AR7240_DDR_TAP_CONTROL1, 0x8); ar7240_reg_wr (AR7240_DDR_TAP_CONTROL2, 0x7); ar7240_reg_wr (AR7240_DDR_TAP_CONTROL3, 0x7); ar7240_usb_initial_config(); ar7240_gpio_config(); return (ar7240_ddr_find_size()); }
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { #if defined(CONFIG_ATHEROS) while (1) { ath_reg_wr(RST_RESET_ADDRESS, RST_RESET_FULL_CHIP_RESET_SET(1)); } #elif defined(CONFIG_INCA_IP) *INCA_IP_WDT_RST_REQ = 0x3f; #elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229) void (*f)(void) = (void *) 0xbfc00000; f(); #elif defined(CONFIG_AR7100) #ifndef COMPRESSED_UBOOT fprintf(stdout, "\nResetting...\n"); #endif /* #ifndef COMPRESSED_UBOOT */ for (;;) { ar7100_reg_wr(AR7100_RESET, (AR7100_RESET_FULL_CHIP | AR7100_RESET_DDR)); } #elif defined(CONFIG_AR7240) #ifndef COMPRESSED_UBOOT fprintf(stdout, "\nResetting...\n"); #endif /* #ifndef COMPRESSED_UBOOT */ for (;;) { #ifdef CONFIG_WASP if (ar7240_reg_rd(AR7240_REV_ID) & 0xf) { ar7240_reg_wr(AR7240_RESET, (AR7240_RESET_FULL_CHIP | AR7240_RESET_DDR)); } else { /* * WAR for full chip reset spi vs. boot-rom selection * bug in wasp 1.0 */ ar7240_reg_wr (AR7240_GPIO_OE, ar7240_reg_rd(AR7240_GPIO_OE) & (~(1 << 17))); } #else ar7240_reg_wr(AR7240_RESET, (AR7240_RESET_FULL_CHIP | AR7240_RESET_DDR)); #endif } #endif #ifndef COMPRESSED_UBOOT fprintf(stderr, "*** reset failed ***\n"); #endif /* #ifndef COMPRESSED_UBOOT */ return 0; }
void cyg_hal_plf_serial_init_channel(void* __ch_data) { CYG_ADDRWORD port; cyg_uint8 _lcr; cyg_uint32 freq; hal_ar7240_sys_frequency(); freq = ar7240_ahb_freq; // Some of the diagnostic print code calls through here with no idea what the ch_data is. // Go ahead and assume it is channels[0]. if (__ch_data == 0) __ch_data = (void*)&channels[0]; port = ((channel_data_t*)__ch_data)->base; /* * undocumented. confirm, why write to GPIO for uart? */ ar7240_reg_wr(AR7240_GPIO_OE, 0xcff); ar7240_reg_wr(AR7240_GPIO_OUT, 0x3b); ar7240_reg_wr(AR7240_GPIO_FUNCTIONS, (ar7240_reg_rd(AR7240_GPIO_FUNCTIONS) | 0x48002)); ar7240_reg_wr(AR7240_GPIO_OUT, 0x2f); // Disable port interrupts while changing hardware HAL_WRITE_UINT32(port+SER_16550_IER, 0); // Set databits, stopbits and parity. _lcr = LCR_WL8 | LCR_SB1 | LCR_PN; HAL_WRITE_UINT32(port+SER_16550_LCR, _lcr); // Set baud rate. cyg_hal_plf_serial_set_baud(port, freq / (16 * CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD)); // Enable and clear FIFO HAL_WRITE_UINT32(port+SER_16550_FCR, (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT)); #ifdef NOTANYMORE // enable RTS to keep host side happy. Also allow interrupts HAL_WRITE_UINT32( port+SER_16550_MCR, MCR_DTR | MCR_RTS | MCR_INT); #endif // Don't allow interrupts. HAL_WRITE_UINT32(port+SER_16550_IER, 0); }
void ath_set_tuning_caps(void){ typedef struct { u_int8_t pad[0x28]; u_int8_t params_for_tuning_caps[2]; u_int8_t featureEnable; } __attribute__((__packed__)) ar9300_eeprom_t; ar9300_eeprom_t *eep = (ar9300_eeprom_t *)WLANCAL; uint32_t val = 0; /* checking feature enable bit 6 and caldata is valid */ if((eep->featureEnable & 0x40) && (eep->pad[0x0] != 0xff)){ /* xtal_capin -bit 17:23 and xtag_capout -bit 24:30*/ val = (eep->params_for_tuning_caps[0] & 0x7f) << 17; val |= (eep->params_for_tuning_caps[0] & 0x7f) << 24; } else { /* default when no caldata available*/ /* checking clock in bit 4 */ if(ar7240_reg_rd(RST_BOOTSTRAP_ADDRESS) & 0x10){ val = (0x1020 << 17); /*default 0x2040 for 40Mhz clock*/ } else { val = (0x2040 << 17); /*default 0x4080 for 25Mhz clock*/ } } val |= (ar7240_reg_rd(XTAL_ADDRESS) & (((1 << 17) - 1) | (1 << 31))); ar7240_reg_wr(XTAL_ADDRESS, val); //prmsg("Setting 0xb8116290 to 0x%x\n", val); return; }
void ar7240_led_toggle(void) { unsigned int gpio; gpio = ar7240_reg_rd(AR7240_GPIO_OUT); #ifdef CONFIG_PID_MR302001 gpio ^= 1 << GPIO_WPS_LED_BIT; #endif #if defined(CONFIG_PID_WR70301) || defined(CONFIG_PID_WR720N03CH) gpio ^= 1 << GPIO_SYS_LED_BIT; #endif #ifdef CONFIG_PID_MR304001 gpio ^= 1 << GPIO_INTERNET_LED_BIT; #endif #ifdef CONFIG_PID_MR10U01 gpio ^= 1 << GPIO_SYS_LED_BIT; #endif #if defined(CONFIG_PID_WR740N04) || defined(CONFIG_PID_MR322002) gpio ^= 1 << GPIO_SYS_LED_BIT; #endif ar7240_reg_wr(AR7240_GPIO_OUT, gpio); }
void led_toggle(void){ unsigned int gpio; gpio = ar7240_reg_rd(AR7240_GPIO_OUT); #if defined(CONFIG_FOR_OMY) gpio ^= 1 << GPIO_SYS_LED_BIT; #elif defined(CONFIG_FOR_TPLINK_MR3020_V1) gpio ^= 1 << GPIO_WPS_LED_BIT; #elif defined(CONFIG_FOR_TPLINK_WR703N_V1) || defined(CONFIG_FOR_TPLINK_WR720N_V3) || defined(CONFIG_FOR_TPLINK_WR710N_V1) gpio ^= 1 << GPIO_SYS_LED_BIT; #elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2) gpio ^= 1 << GPIO_INTERNET_LED_BIT; #elif defined(CONFIG_FOR_TPLINK_MR10U_V1) || defined(CONFIG_FOR_TPLINK_MR13U_V1) gpio ^= 1 << GPIO_SYS_LED_BIT; #elif defined(CONFIG_FOR_TPLINK_WR740N_V4) || defined(CONFIG_FOR_TPLINK_MR3220_V2) gpio ^= 1 << GPIO_SYS_LED_BIT; #elif defined(CONFIG_FOR_DLINK_DIR505_A1) gpio ^= 1 << GPIO_SYS_LED_BIT; #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV) gpio ^= 1 << GPIO_SYS_LED_BIT; #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) gpio ^= 1 << GPIO_WLAN_LED_BIT; #elif defined(CONFIG_FOR_DRAGINO_V2) || defined(CONFIG_FOR_MESH_POTATO_V2) gpio ^= 1 << GPIO_WLAN_LED_BIT; #elif defined(CONFIG_FOR_GL_INET) gpio ^= 1 << GPIO_WLAN_LED_BIT; #else #error "Custom GPIO in leg_toggle() not defined!" #endif ar7240_reg_wr(AR7240_GPIO_OUT, gpio); }
int write_buff(flash_info_t *info, uchar *src, ulong dst, ulong len) { uint32_t val; dst = dst - CFG_FLASH_BASE; printf("write len: %lu dst: 0x%x src: %p\n", len, dst, src); for (; len; len--, dst++, src++) { ar7240_spi_write_enable(); // dont move this above 'for' ar7240_spi_bit_banger(AR7240_SPI_CMD_PAGE_PROG); ar7240_spi_send_addr(dst); val = *src & 0xff; ar7240_spi_bit_banger(val); ar7240_spi_go(); ar7240_spi_poll(); } /* * Disable the Function Select * Without this we can't read from the chip again */ ar7240_reg_wr(AR7240_SPI_FS, 0); if (len) { // how to differentiate errors ?? return ERR_PROG_ERROR; } else { return ERR_OK; } }
static int ar7240_pci_write_config(struct pci_controller *hose, pci_dev_t dev, int where, uint32_t value) { ar7240_reg_wr((AR7240_PCI_DEV_CFGBASE + where),value); return 0; }
void glzt_set_gpio_to_l3(void) { /*Set GPIO control wm8978 */ ar7240_reg_rmw_set(RST_RESET,AR7240_RESET_I2S|AR7240_RESET_PCI_CORE); udelay(500); ar7240_reg_wr(AR7240_GPIO_OE,(IIS_CONTROL_CSB|IIS_CONTROL_SDIN|IIS_CONTROL_SCLK)); }
int ar7240_mem_config(void) { /* Default tap values for starting the tap_init*/ ar7240_reg_wr(AR7240_DDR_TAP_CONTROL0, CFG_DDR_TAP0_VAL); ar7240_reg_wr(AR7240_DDR_TAP_CONTROL1, CFG_DDR_TAP1_VAL); ar7240_gpio_config(); ar7240_all_led_off(); // TODO: check if this is necessary for USB initialization //ar7240_usb_initial_config(); //ar7240_usb_otp_config(); hornet_ddr_tap_init(); // return memory size return (ar7240_ddr_find_size()); }
int board_set_gpio_regs(unsigned int addr, unsigned int set, unsigned int clear) { if ((addr >= 0x18040000) && (addr <= 0x18040044) && (addr % 4 == 0)){ ar7240_reg_wr(addr, ((ar7240_reg_rd(addr) | set) & (~clear))); return 0; } return 1; }
/* Set the timeout value in the watchdog register */ static inline void ar7240_set_wd_timer(uint32_t usec /* micro seconds */) { usec = usec * (wdt->clk_freq / USEC_PER_SEC); wddbg("%s: 0x%08x\n", __func__, usec); ar7240_reg_wr(AR7240_WATCHDOG_TMR, usec); }
void all_led_on(void){ unsigned int gpio; gpio = ar7240_reg_rd(AR7240_GPIO_OUT); #if defined(CONFIG_FOR_OMY) SETBITVAL(gpio, GPIO_WPS_LED_BIT, GPIO_SYS_LED_ON); #elif defined(CONFIG_FOR_TPLINK_MR3020_V1) SETBITVAL(gpio, GPIO_WPS_LED_BIT, GPIO_WPS_LED_ON); SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON); SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON); SETBITVAL(gpio, GPIO_ETH_LED_BIT, GPIO_ETH_LED_ON); #elif defined(CONFIG_FOR_TPLINK_WR703N_V1) || defined(CONFIG_FOR_TPLINK_WR720N_V3) || defined (CONFIG_FOR_TPLINK_WR710N_V1) SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON); #elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2) SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON); SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON); SETBITVAL(gpio, GPIO_ETH_LED_BIT, GPIO_ETH_LED_ON); #elif defined(CONFIG_FOR_TPLINK_MR10U_V1) || defined(CONFIG_FOR_TPLINK_MR13U_V1) SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON); #elif defined(CONFIG_FOR_TPLINK_WR740N_V4) || defined(CONFIG_FOR_TPLINK_MR3220_V2) SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON); SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON); SETBITVAL(gpio, GPIO_LAN1_LED_BIT, GPIO_LAN1_LED_ON); SETBITVAL(gpio, GPIO_LAN2_LED_BIT, GPIO_LAN2_LED_ON); SETBITVAL(gpio, GPIO_LAN3_LED_BIT, GPIO_LAN3_LED_ON); SETBITVAL(gpio, GPIO_LAN4_LED_BIT, GPIO_LAN4_LED_ON); SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON); SETBITVAL(gpio, GPIO_QSS_LED_BIT, GPIO_QSS_LED_ON); #ifdef CONFIG_FOR_TPLINK_MR3220_V2 SETBITVAL(gpio, GPIO_USB_LED_BIT, GPIO_USB_LED_ON); #endif #elif defined(CONFIG_FOR_DLINK_DIR505_A1) SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON); #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV) SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON); SETBITVAL(gpio, GPIO_WAN_LED_BIT, GPIO_WAN_LED_ON); SETBITVAL(gpio, GPIO_LAN1_LED_BIT, GPIO_LAN1_LED_ON); SETBITVAL(gpio, GPIO_LAN2_LED_BIT, GPIO_LAN2_LED_ON); #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON); #elif defined(CONFIG_FOR_DRAGINO_V2) || defined(CONFIG_FOR_MESH_POTATO_V2) SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON); SETBITVAL(gpio, GPIO_WAN_LED_BIT, GPIO_WAN_LED_ON); SETBITVAL(gpio, GPIO_LAN_LED_BIT, GPIO_LAN_LED_ON); SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON); #elif defined(CONFIG_FOR_GL_INET) SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON); SETBITVAL(gpio, GPIO_LAN_LED_BIT, GPIO_LAN_LED_ON); #else #error "Custom GPIO in all_led_on() not defined!" #endif ar7240_reg_wr(AR7240_GPIO_OUT, gpio); }
void led_toggle(void){ unsigned int gpio; gpio = ar7240_reg_rd(AR7240_GPIO_OUT); // SYS LED is connected to GPIO 14 gpio ^= 1 << 14; ar7240_reg_wr(AR7240_GPIO_OUT, gpio); }
void ar7240_gpio_config(void) { /* Disable clock obs * clk_obs1(gpio13/bit8), clk_obs2(gpio14/bit9), clk_obs3(gpio15/bit10), * clk_obs4(gpio16/bit11), clk_obs5(gpio17/bit12) * clk_obs0(gpio1/bit19), 6(gpio11/bit20) */ ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & ~((0x1f<<8)|(0x3<<19)))); /* Enable eth Switch LEDs */ //ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | (0x1f<<3))); /* Clear AR7240_GPIO_FUNC BIT2 to ensure that software can control LED5(GPIO16) and LED6(GPIO17) */ ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & ~(0x1<<2))); /* Set HORNET_BOOTSTRAP_STATUS BIT18 to ensure that software can control GPIO26 and GPIO27 */ //ar7240_reg_wr (HORNET_BOOTSTRAP_STATUS, (ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) | (0x1<<18))); }
void all_led_off(void){ unsigned int gpio; gpio = ar7240_reg_rd(AR7240_GPIO_OUT); // SYS LED (GPIO 14) and WLAN24 (GPIO 13) SETBITVAL(gpio, 14, 1); SETBITVAL(gpio, 13, 1); ar7240_reg_wr(AR7240_GPIO_OUT, gpio); }
void ar7240_gpio_setpin(unsigned int pin, unsigned int to) { //uint32_t r; //r = ar7240_reg_rd(MBOX_INT_STATUS); //ar7240_reg_rmw_clear(AR7240_GPIO_OE,(AR7240_LED_3|AR7240_LED_4|AR7240_LED_5)); unsigned long flags; unsigned long dat; if(to) { local_irq_save(flags); //ar7240_reg_rmw_clear(AR7240_GPIO_OE,(AR7240_LED_3|AR7240_LED_4|AR7240_LED_5)); ar7240_reg_rmw_clear(AR7240_GPIO_OE,(IIS_CONTROL_CSB|IIS_CONTROL_SDIN|IIS_CONTROL_SCLK)); dat = ar7240_reg_rd(AR7240_GPIO_IN); dat |= pin; //ar7240_reg_wr(AR7240_GPIO_OE,(AR7240_LED_3|AR7240_LED_4|AR7240_LED_5)); ar7240_reg_wr(AR7240_GPIO_OE,(IIS_CONTROL_CSB|IIS_CONTROL_SDIN|IIS_CONTROL_SCLK)); ar7240_reg_wr(AR7240_GPIO_OUT,dat); local_irq_restore(flags); } else { local_irq_save(flags); //ar7240_reg_rmw_clear(AR7240_GPIO_OE,(AR7240_LED_3|AR7240_LED_4|AR7240_LED_5)); ar7240_reg_rmw_clear(AR7240_GPIO_OE,(IIS_CONTROL_CSB|IIS_CONTROL_SDIN|IIS_CONTROL_SCLK)); dat = ar7240_reg_rd(AR7240_GPIO_IN); dat &= ~(pin); //ar7240_reg_wr(AR7240_GPIO_OE,(AR7240_LED_3|AR7240_LED_4|AR7240_LED_5)); ar7240_reg_wr(AR7240_GPIO_OE,(IIS_CONTROL_CSB|IIS_CONTROL_SDIN|IIS_CONTROL_SCLK)); ar7240_reg_wr(AR7240_GPIO_OUT,dat); local_irq_restore(flags); } }
int ar7240_mem_config(void){ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #ifndef COMPRESSED_UBOOT hornet_ddr_init(); #endif /* Default tap values for starting the tap_init*/ ar7240_reg_wr(AR7240_DDR_TAP_CONTROL0, CFG_DDR_TAP0_VAL); ar7240_reg_wr(AR7240_DDR_TAP_CONTROL1, CFG_DDR_TAP1_VAL); #endif gpio_config(); all_led_off(); #ifndef CONFIG_SKIP_LOWLEVEL_INIT hornet_ddr_tap_init(); #endif // return memory size return(ar7240_ddr_find_size()); }
int ar7240_mem_config(void) { unsigned int tap_val1, tap_val2; ar7240_ddr_initial_config(CFG_DDR_REFRESH_VAL); /* Default tap values for starting the tap_init*/ ar7240_reg_wr (AR7240_DDR_TAP_CONTROL0, 0x8); ar7240_reg_wr (AR7240_DDR_TAP_CONTROL1, 0x9); ar7240_ddr_tap_init(); tap_val1 = ar7240_reg_rd(0xb800001c); tap_val2 = ar7240_reg_rd(0xb8000020); printf("#### TAP VALUE 1 = %x, 2 = %x\n",tap_val1, tap_val2); ar7240_usb_initial_config(); ar7240_gpio_config(); return (ar7240_ddr_find_size()); }