static int ar8035_phy_fixup(struct phy_device *dev) { u16 val; /* Ar803x phy SmartEEE feature cause link status generates glitch, * which cause ethernet link down/up issue, so disable SmartEEE */ phy_write(dev, 0xd, 0x3); phy_write(dev, 0xe, 0x805d); phy_write(dev, 0xd, 0x4003); val = phy_read(dev, 0xe); phy_write(dev, 0xe, val & ~(1 << 8)); /* * Enable 125MHz clock from CLK_25M on the AR8031. This * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad. * Also, introduce a tx clock delay. * * This is the same as is the AR8031 fixup. */ ar8031_phy_fixup(dev); /*check phy power*/ val = phy_read(dev, 0x0); if (val & BMCR_PDOWN) phy_write(dev, 0x0, val & ~BMCR_PDOWN); return 0; }
int board_phy_config(struct phy_device *phydev) { ar8031_phy_fixup(phydev); if (phydev->drv->config) phydev->drv->config(phydev); return 0; }