int __init arch_timer_sched_clock_init(void) { if (arch_timer_get_rate() == 0) return -ENXIO; setup_sched_clock(arch_timer_read_counter_u32, 32, arch_timer_get_rate()); return 0; }
static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) { int rt = ESR_ELx_SYS64_ISS_RT(esr); pt_regs_write_reg(regs, rt, arch_timer_get_rate()); arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); }
static void __init arch_timer_delay_timer_register(void) { /* Use the architected timer for the delay loop. */ arch_delay_timer.read_current_timer = arch_timer_read_counter_long; arch_delay_timer.freq = arch_timer_get_rate(); register_current_timer_delay(&arch_delay_timer); }
int __init arch_timer_arch_init(void) { u32 arch_timer_rate = arch_timer_get_rate(); if (arch_timer_rate == 0) return -ENXIO; arch_timer_delay_timer_register(); return 0; }
void __init time_init(void) { u32 arch_timer_rate; clocksource_of_init(); arch_timer_rate = arch_timer_get_rate(); if (!arch_timer_rate) panic("Unable to initialise architected timer.\n"); /* Calibrate the delay loop directly */ lpj_fine = arch_timer_rate / HZ; }
int __init arch_timer_arch_init(void) { u32 arch_timer_rate = arch_timer_get_rate(); if (arch_timer_rate == 0) return -ENXIO; arch_timer_delay_timer_register(); /* Cache the sched_clock multiplier to save a divide in the hot path. */ sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate); return 0; }
void __init time_init(void) { u32 arch_timer_rate; of_clk_init(NULL); clocksource_of_init(); tick_setup_hrtimer_broadcast(); arch_timer_rate = arch_timer_get_rate(); if (!arch_timer_rate) panic("Unable to initialise architected timer.\n"); /* Calibrate the delay loop directly */ lpj_fine = arch_timer_rate / HZ; }
static void __init arch_timer_init(struct device_node *np) { u32 freq; int i; if (arch_timer_get_rate()) { pr_warn("arch_timer: multiple nodes in dt, skipping\n"); return; } /* Try to determine the frequency from the device tree or CNTFRQ */ if (!of_property_read_u32(np, "clock-frequency", &freq)) arch_timer_rate = freq; for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) arch_timer_ppi[i] = irq_of_parse_and_map(np, i); of_node_put(np); /* * If HYP mode is available, we know that the physical timer * has been configured to be accessible from PL1. Use it, so * that a guest can use the virtual timer instead. * * If no interrupt provided for virtual timer, we'll have to * stick to the physical timer. It'd better be accessible... */ if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) { arch_timer_use_virtual = false; if (!arch_timer_ppi[PHYS_SECURE_PPI] || !arch_timer_ppi[PHYS_NONSECURE_PPI]) { pr_warn("arch_timer: No interrupt available, giving up\n"); return; } } arch_timer_register(); arch_timer_arch_init(); }