static void BSP_START_SECTION lpc32xx_mmu_and_cache_setup(void)
{
uint32_t ctrl = 0;
/* Disable MMU and cache, basic settings */
ctrl = arm_cp15_get_control();
ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_R | ARM_CP15_CTRL_C
| ARM_CP15_CTRL_V | ARM_CP15_CTRL_M);
ctrl |= ARM_CP15_CTRL_S | ARM_CP15_CTRL_A;
arm_cp15_set_control(ctrl);
arm_cp15_cache_invalidate();
arm_cp15_tlb_invalidate();
#ifndef LPC32XX_DISABLE_MMU
lpc32xx_setup_translation_table_and_enable_mmu(ctrl);
#endif
}
static BSP_START_TEXT_SECTION void setup_mmu_and_cache(void)
{
uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
ARM_CP15_CTRL_I | ARM_CP15_CTRL_R | ARM_CP15_CTRL_C
| ARM_CP15_CTRL_V | ARM_CP15_CTRL_M,
ARM_CP15_CTRL_S | ARM_CP15_CTRL_A
);
arm_cp15_cache_invalidate();
#ifndef LPC32XX_DISABLE_MMU
arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
ctrl,
(uint32_t *) bsp_translation_table_base,
LPC32XX_MMU_CLIENT_DOMAIN,
&lpc32xx_mmu_config_table [0],
RTEMS_ARRAY_SIZE(lpc32xx_mmu_config_table)
);
#endif
}
void mmu_init(mmu_sect_map_t *map)
{
mmu_lvl1_t *lvl1_base;
int i;
/* flush the cache and TLB */
arm_cp15_cache_invalidate();
arm_cp15_tlb_invalidate();
/* set manage mode access for all domains */
arm_cp15_set_domain_access_control(0xffffffff);
lvl1_base = (mmu_lvl1_t *)&_ttbl_base;
/* set up the trans table */
mmu_set_map_inval(lvl1_base);
arm_cp15_set_translation_table_base(lvl1_base);
/* create a 1:1 mapping of the entire address space */
i = 0;
while(map[i].size != 0) {
int c = 0; /* to avoid uninitialized warnings */
int b = 0; /* to avoid uninitialized warnings */
int pbase;
int vbase;
int sects;
switch (map[i].cache_flags) {
case MMU_CACHE_NONE:
c = 0;
b = 0;
break;
case MMU_CACHE_BUFFERED:
c = 0;
b = 1;
break;
case MMU_CACHE_WTHROUGH:
c = 1;
b = 0;
break;
case MMU_CACHE_WBACK:
c = 1;
b = 1;
break;
}
pbase = (map[i].paddr & 0xfff00000) >> 20;
vbase = (map[i].vaddr & 0xfff00000) >> 20;
sects = map[i].size;
while (sects > 0) {
lvl1_base[vbase] = MMU_SET_LVL1_SECT(pbase << 20,
MMU_SECT_AP_ALL,
0,
c,
b);
pbase++;
vbase++;
sects--;
}
i++;
}
/* flush the cache and TLB */
arm_cp15_cache_invalidate();
arm_cp15_tlb_invalidate();
/* I & D caches turned on */
arm_cp15_set_control(MMU_CTRL_DEFAULT |
MMU_CTRL_D_CACHE_EN |
MMU_CTRL_I_CACHE_EN |
MMU_CTRL_ALIGN_FAULT_EN |
MMU_CTRL_LITTLE_ENDIAN |
MMU_CTRL_MMU_EN);
return;
}
