void rpi_start_rtems_on_secondary_processor(void) { uint32_t ctrl; ctrl = arm_cp15_start_setup_mmu_and_cache( 0, ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z ); rpi_ipi_initialize(); arm_cp15_set_domain_access_control( ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT) ); /* FIXME: Sharing the translation table between processors is brittle */ arm_cp15_set_translation_table_base( (uint32_t *) bsp_translation_table_base ); arm_cp15_tlb_invalidate(); ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; ctrl &= ~ARM_CP15_CTRL_V; arm_cp15_set_control(ctrl); _SMP_Start_multitasking_on_secondary_processor(); }
BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void) { uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache( ARM_CP15_CTRL_A, ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z ); arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( ctrl, (uint32_t *) bsp_translation_table_base, ARM_MMU_DEFAULT_CLIENT_DOMAIN, &zynq_mmu_config_table[0], RTEMS_ARRAY_SIZE(zynq_mmu_config_table) ); }
static BSP_START_TEXT_SECTION void setup_mmu_and_cache(void) { uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache( ARM_CP15_CTRL_I | ARM_CP15_CTRL_R | ARM_CP15_CTRL_C | ARM_CP15_CTRL_V | ARM_CP15_CTRL_M, ARM_CP15_CTRL_S | ARM_CP15_CTRL_A ); arm_cp15_cache_invalidate(); #ifndef LPC32XX_DISABLE_MMU arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( ctrl, (uint32_t *) bsp_translation_table_base, LPC32XX_MMU_CLIENT_DOMAIN, &lpc32xx_mmu_config_table [0], RTEMS_ARRAY_SIZE(lpc32xx_mmu_config_table) ); #endif }