int arm_set_cpu_off(uint64_t cpuid) { CPUState *target_cpu_state; ARMCPU *target_cpu; DPRINTF("cpu %" PRId64 "\n", cpuid); /* change to the cpu we are powering up */ target_cpu_state = arm_get_cpu_by_id(cpuid); if (!target_cpu_state) { return QEMU_ARM_POWERCTL_INVALID_PARAM; } target_cpu = ARM_CPU(target_cpu_state); if (target_cpu->powered_off) { qemu_log_mask(LOG_GUEST_ERROR, "[ARM]%s: CPU %" PRId64 " is already off\n", __func__, cpuid); return QEMU_ARM_POWERCTL_IS_OFF; } target_cpu->powered_off = true; target_cpu_state->halted = 1; target_cpu_state->exception_index = EXCP_HLT; cpu_loop_exit(target_cpu_state); /* notreached */ return QEMU_ARM_POWERCTL_RET_SUCCESS; }
int arm_reset_cpu(uint64_t cpuid) { CPUState *target_cpu_state; ARMCPU *target_cpu; DPRINTF("cpu %" PRId64 "\n", cpuid); /* change to the cpu we are resetting */ target_cpu_state = arm_get_cpu_by_id(cpuid); if (!target_cpu_state) { return QEMU_ARM_POWERCTL_INVALID_PARAM; } target_cpu = ARM_CPU(target_cpu_state); if (target_cpu->powered_off) { qemu_log_mask(LOG_GUEST_ERROR, "[ARM]%s: CPU %" PRId64 " is off\n", __func__, cpuid); return QEMU_ARM_POWERCTL_IS_OFF; } /* Reset the cpu */ cpu_reset(target_cpu_state); return QEMU_ARM_POWERCTL_RET_SUCCESS; }
int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id, uint32_t target_el, bool target_aa64) { CPUState *target_cpu_state; ARMCPU *target_cpu; DPRINTF("cpu %" PRId64 " (EL %d, %s) @ 0x%" PRIx64 " with R0 = 0x%" PRIx64 "\n", cpuid, target_el, target_aa64 ? "aarch64" : "aarch32", entry, context_id); /* requested EL level need to be in the 1 to 3 range */ assert((target_el > 0) && (target_el < 4)); if (target_aa64 && (entry & 3)) { /* * if we are booting in AArch64 mode then "entry" needs to be 4 bytes * aligned. */ return QEMU_ARM_POWERCTL_INVALID_PARAM; } /* Retrieve the cpu we are powering up */ target_cpu_state = arm_get_cpu_by_id(cpuid); if (!target_cpu_state) { /* The cpu was not found */ return QEMU_ARM_POWERCTL_INVALID_PARAM; } target_cpu = ARM_CPU(target_cpu_state); if (!target_cpu->powered_off) { qemu_log_mask(LOG_GUEST_ERROR, "[ARM]%s: CPU %" PRId64 " is already on\n", __func__, cpuid); return QEMU_ARM_POWERCTL_ALREADY_ON; } /* * The newly brought CPU is requested to enter the exception level * "target_el" and be in the requested mode (AArch64 or AArch32). */ if (((target_el == 3) && !arm_feature(&target_cpu->env, ARM_FEATURE_EL3)) || ((target_el == 2) && !arm_feature(&target_cpu->env, ARM_FEATURE_EL2))) { /* * The CPU does not support requested level */ return QEMU_ARM_POWERCTL_INVALID_PARAM; } if (!target_aa64 && arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64)) { /* * For now we don't support booting an AArch64 CPU in AArch32 mode * TODO: We should add this support later */ qemu_log_mask(LOG_UNIMP, "[ARM]%s: Starting AArch64 CPU %" PRId64 " in AArch32 mode is not supported yet\n", __func__, cpuid); return QEMU_ARM_POWERCTL_INVALID_PARAM; } /* Initialize the cpu we are turning on */ cpu_reset(target_cpu_state); target_cpu->powered_off = false; target_cpu_state->halted = 0; if (target_aa64) { if ((target_el < 3) && arm_feature(&target_cpu->env, ARM_FEATURE_EL3)) { /* * As target mode is AArch64, we need to set lower * exception level (the requested level 2) to AArch64 */ target_cpu->env.cp15.scr_el3 |= SCR_RW; } if ((target_el < 2) && arm_feature(&target_cpu->env, ARM_FEATURE_EL2)) { /* * As target mode is AArch64, we need to set lower * exception level (the requested level 1) to AArch64 */ target_cpu->env.cp15.hcr_el2 |= HCR_RW; } target_cpu->env.pstate = aarch64_pstate_mode(target_el, true); } else { /* We are requested to boot in AArch32 mode */ static uint32_t mode_for_el[] = { 0, ARM_CPU_MODE_SVC, ARM_CPU_MODE_HYP, ARM_CPU_MODE_SVC }; cpsr_write(&target_cpu->env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); } if (target_el == 3) { /* Processor is in secure mode */ target_cpu->env.cp15.scr_el3 &= ~SCR_NS; } else { /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |= SCR_NS; } /* We check if the started CPU is now at the correct level */ assert(target_el == arm_current_el(&target_cpu->env)); if (target_aa64) { target_cpu->env.xregs[0] = context_id; target_cpu->env.thumb = false; } else { target_cpu->env.regs[0] = context_id; target_cpu->env.thumb = entry & 1; entry &= 0xfffffffe; } /* Start the new CPU at the requested address */ cpu_set_pc(target_cpu_state, entry); /* We are good to go */ return QEMU_ARM_POWERCTL_RET_SUCCESS; }
void arm_handle_psci_call(ARMCPU *cpu) { /* * This function partially implements the logic for dispatching Power State * Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b), * to the extent required for bringing up and taking down secondary cores, * and for handling reset and poweroff requests. * Additional information about the calling convention used is available in * the document 'SMC Calling Convention' (ARM DEN 0028) */ CPUARMState *env = &cpu->env; uint64_t param[4]; uint64_t context_id, mpidr; target_ulong entry; int32_t ret = 0; int i; for (i = 0; i < 4; i++) { /* * All PSCI functions take explicit 32-bit or native int sized * arguments so we can simply zero-extend all arguments regardless * of which exact function we are about to call. */ param[i] = is_a64(env) ? env->xregs[i] : env->regs[i]; } if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) { ret = QEMU_PSCI_RET_INVALID_PARAMS; goto err; } switch (param[0]) { CPUState *target_cpu_state; ARMCPU *target_cpu; case QEMU_PSCI_0_2_FN_PSCI_VERSION: ret = QEMU_PSCI_0_2_RET_VERSION_0_2; break; case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ break; case QEMU_PSCI_0_2_FN_AFFINITY_INFO: case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: mpidr = param[1]; switch (param[2]) { case 0: target_cpu_state = arm_get_cpu_by_id(mpidr); if (!target_cpu_state) { ret = QEMU_PSCI_RET_INVALID_PARAMS; break; } target_cpu = ARM_CPU(target_cpu_state); g_assert(qemu_mutex_iothread_locked()); ret = target_cpu->power_state; break; default: /* Everything above affinity level 0 is always on. */ ret = 0; } break; case QEMU_PSCI_0_2_FN_SYSTEM_RESET: qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); /* QEMU reset and shutdown are async requests, but PSCI * mandates that we never return from the reset/shutdown * call, so power the CPU off now so it doesn't execute * anything further. */ goto cpu_off; case QEMU_PSCI_0_2_FN_SYSTEM_OFF: qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); goto cpu_off; case QEMU_PSCI_0_1_FN_CPU_ON: case QEMU_PSCI_0_2_FN_CPU_ON: case QEMU_PSCI_0_2_FN64_CPU_ON: { /* The PSCI spec mandates that newly brought up CPUs start * in the highest exception level which exists and is enabled * on the calling CPU. Since the QEMU PSCI implementation is * acting as a "fake EL3" or "fake EL2" firmware, this for us * means that we want to start at the highest NS exception level * that we are providing to the guest. * The execution mode should be that which is currently in use * by the same exception level on the calling CPU. * The CPU should be started with the context_id value * in x0 (if AArch64) or r0 (if AArch32). */ int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; bool target_aarch64 = arm_el_is_aa64(env, target_el); mpidr = param[1]; entry = param[2]; context_id = param[3]; ret = arm_set_cpu_on(mpidr, entry, context_id, target_el, target_aarch64); break; } case QEMU_PSCI_0_1_FN_CPU_OFF: case QEMU_PSCI_0_2_FN_CPU_OFF: goto cpu_off; case QEMU_PSCI_0_1_FN_CPU_SUSPEND: case QEMU_PSCI_0_2_FN_CPU_SUSPEND: case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: /* Affinity levels are not supported in QEMU */ if (param[1] & 0xfffe0000) { ret = QEMU_PSCI_RET_INVALID_PARAMS; break; } /* Powerdown is not supported, we always go into WFI */ if (is_a64(env)) { env->xregs[0] = 0; } else { env->regs[0] = 0; } helper_wfi(env, 4); break; case QEMU_PSCI_0_1_FN_MIGRATE: case QEMU_PSCI_0_2_FN_MIGRATE: ret = QEMU_PSCI_RET_NOT_SUPPORTED; break; default: g_assert_not_reached(); } err: if (is_a64(env)) { env->xregs[0] = ret; } else { env->regs[0] = ret; } return; cpu_off: ret = arm_set_cpu_off(cpu->mp_affinity); /* notreached */ /* sanity check in case something failed */ assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); }