void arm_irq_setup(void) { extern u32 _start_vect[]; u32 *vectors = (u32 *)NULL; u32 *vectors_data = vectors + CPU_IRQ_NR; int vec; /* * Loop through the vectors we're taking over, and copy the * vector's insn and data word. */ for (vec = 0; vec < CPU_IRQ_NR; vec++) { vectors[vec] = _start_vect[vec]; vectors_data[vec] = _start_vect[vec+CPU_IRQ_NR]; } /* * Check if verctors are set properly */ for (vec = 0; vec < CPU_IRQ_NR; vec++) { if ((vectors[vec] != _start_vect[vec]) || (vectors_data[vec] != _start_vect[vec+CPU_IRQ_NR])) { /* Hang */ while(1); } } /* * Reset irq handlers */ for (vec = 0; vec < NR_IRQS_PBA8; vec++) { irq_hndls[vec] = NULL; } /* * Initialize Generic Interrupt Controller */ vec = arm_gic_dist_init(0, REALVIEW_PBA8_GIC_DIST_BASE, IRQ_PBA8_GIC_START); if (vec) { while(1); } vec = arm_gic_cpu_init(0, REALVIEW_PBA8_GIC_CPU_BASE); if (vec) { while(1); } }
/** * This function will initialize hardware interrupt */ void rt_hw_interrupt_init(void) { rt_uint32_t gic_cpu_base; rt_uint32_t gic_dist_base; /* initialize vector table */ rt_hw_vector_init(); /* initialize exceptions table */ rt_memset(isr_table, 0x00, sizeof(isr_table)); /* initialize ARM GIC */ gic_dist_base = REALVIEW_GIC_DIST_BASE; gic_cpu_base = REALVIEW_GIC_CPU_BASE; arm_gic_dist_init(0, gic_dist_base, 0); arm_gic_cpu_init(0, gic_cpu_base); }
/** * This function will initialize hardware interrupt */ void rt_hw_interrupt_init(void) { rt_uint32_t gic_cpu_base; rt_uint32_t gic_dist_base; /* initialize vector table */ rt_hw_vector_init(); /* initialize exceptions table */ rt_memset(isr_table, 0x00, sizeof(isr_table)); /* initialize ARM GIC */ gic_dist_base = REALVIEW_GIC_DIST_BASE; gic_cpu_base = REALVIEW_GIC_CPU_BASE; arm_gic_dist_init(0, gic_dist_base, 0); arm_gic_cpu_init(0, gic_cpu_base); /*arm_gic_dump_type(0);*/ /* init interrupt nest, and context in thread sp */ rt_interrupt_nest = 0; rt_interrupt_from_thread = 0; rt_interrupt_to_thread = 0; rt_thread_switch_interrupt_flag = 0; }