void arm_mmu_init(void)
{
int i;
/* set some mmu specific control bits */
arm_write_cr1(arm_read_cr1() & ~((1<<29)|(1<<28)|(1<<0))); // access flag disabled, TEX remap disabled, mmu disabled
/* set up an identity-mapped translation table with cache disabled */
for (i=0; i < 4096; i++) {
#ifdef WITH_DMA_ZONE
#if defined(PLATFORM_TCC892X)
arm_mmu_map_section(i * MB, i * MB, MMU_FLAG_READWRITE | MMU_FLAG_CACHED | MMU_FLAG_BUFFERED);
#else
arm_mmu_map_section(i * MB, i * MB, MMU_FLAG_READWRITE | MMU_FLAG_CACHED);
#endif
#else
arm_mmu_map_section(i * MB, i * MB, MMU_FLAG_READWRITE); // map everything uncached
#endif
}
/* set up the translation table base */
arm_write_ttbr((uint32_t)tt);
/* set up the domain access register */
arm_write_dacr(0x00000001);
/* turn on the mmu */
arm_write_cr1(arm_read_cr1() | 0x1);
}
void arm_mmu_init(void)
{
/* set some mmu specific control bits */
arm_write_sctlr(arm_read_sctlr() & ~((1<<29)|(1<<28)|(1<<0))); // access flag disabled, TEX remap disabled, mmu disabled
/* set up an identity-mapped translation table with cache disabled */
for (addr_t i=0; i < 4096; i++) {
arm_mmu_map_section(i * MB, i * MB, MMU_FLAG_READWRITE); // map everything uncached
}
/* set up the translation table base */
arm_write_ttbr((uint32_t)tt);
/* set up the domain access register */
arm_write_dacr(0x00000001);
/* turn on the mmu */
arm_write_sctlr(arm_read_sctlr() | 0x1);
}