static inline u32 armv8pmu_read_counter(struct perf_event *event) { struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; u32 value = 0; if (!armv8pmu_counter_valid(cpu_pmu, idx)) pr_err("CPU%u reading wrong counter %d\n", smp_processor_id(), idx); else if (idx == ARMV8_IDX_CYCLE_COUNTER) value = read_sysreg(pmccntr_el0); else if (armv8pmu_select_counter(idx) == idx) value = read_sysreg(pmxevcntr_el0); return value; }
static inline void armv8pmu_write_counter(struct perf_event *event, u32 value) { struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; if (!armv8pmu_counter_valid(cpu_pmu, idx)) pr_err("CPU%u writing wrong counter %d\n", smp_processor_id(), idx); else if (idx == ARMV8_IDX_CYCLE_COUNTER) { /* * Set the upper 32bits as this is a 64bit counter but we only * count using the lower 32bits and we want an interrupt when * it overflows. */ u64 value64 = 0xffffffff00000000ULL | value; write_sysreg(value64, pmccntr_el0); } else if (armv8pmu_select_counter(idx) == idx) write_sysreg(value, pmxevcntr_el0); }
static inline void armv8pmu_write_counter(struct perf_event *event, u64 value) { struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; if (!armv8pmu_counter_valid(cpu_pmu, idx)) pr_err("CPU%u writing wrong counter %d\n", smp_processor_id(), idx); else if (idx == ARMV8_IDX_CYCLE_COUNTER) { /* * The cycles counter is really a 64-bit counter. * When treating it as a 32-bit counter, we only count * the lower 32 bits, and set the upper 32-bits so that * we get an interrupt upon 32-bit overflow. */ if (!armv8pmu_event_is_64bit(event)) value |= 0xffffffff00000000ULL; write_sysreg(value, pmccntr_el0); } else armv8pmu_write_hw_counter(event, value); }