Esempio n. 1
0
/*
 * platform_configure_usb - usb configuration based on platform type.
 * @bcm1_usb2_ctl:	value for the BCM1_USB2_CTL register, which is
 *			quirky
 */
static void __init platform_configure_usb(void)
{
	u32 bcm1_usb2_ctl;

	if (usb_configured)
		return;

	switch (asic) {
	case ASIC_ZEUS:
	case ASIC_CRONUS:
	case ASIC_CRONUSLITE:
		fs_update(0x0000, 0x11, 0x02, 0);
		bcm1_usb2_ctl = 0x803;
		break;

	case ASIC_CALLIOPE:
		fs_update(0x0000, 0x11, 0x02, 1);

		switch (platform_family) {
		case FAMILY_1500VZE:
			break;

		case FAMILY_1500VZF:
			usb_eye_configure(0x003c0000);
			break;

		default:
			usb_eye_configure(0x00300000);
			break;
		}

		bcm1_usb2_ctl = 0x803;
		break;

	default:
		pr_err("Unknown ASIC type: %d\n", asic);
		break;
	}

	/* turn on USB power */
	asic_write(0, usb2_strap);
	/* Enable all OHCI interrupts */
	asic_write(bcm1_usb2_ctl, usb2_control);
	/* USB2_STBUS_OBC store32/load32 */
	asic_write(3, usb2_stbus_obc);
	/* USB2_STBUS_MESS_SIZE 2 packets */
	asic_write(1, usb2_stbus_mess_size);
	/* USB2_STBUS_CHUNK_SIZE 2 packets */
	asic_write(1, usb2_stbus_chunk_size);

	usb_configured = true;
}
static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits,
	u32 disable_div_by_3, u32 standby)
{
	u32 val;

	val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) |
		((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) |
		(pe_bits << QAM_FS_PE_SHIFT) |
		QAM_FS_ENABLE_OUTPUT |
		standby |
		disable_div_by_3);
	asic_write(val, fs432x4b4_usb_ctl);
	asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl);
	asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS,
		fs432x4b4_usb_ctl);
}
static void usb_eye_configure(u32 set, u32 clear)
{
	u32 old;

	old = asic_read(crt_spare);
	old |= set;
	old &= ~clear;
	asic_write(old, crt_spare);
}
Esempio n. 4
0
/*
 *
 * Platform Configuration and Device Initialization
 *
 */
static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3)
{
	int en_prg, byp, pwr, nsb, val;
	int sout;

	sout = 1;
	en_prg = 1;
	byp = 0;
	nsb = 1;
	pwr = 1;

	val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) |
		(nsb<<1) | (disable_div_by_3<<5));

	asic_write(val, usb_fs);
	asic_write(val | (en_prg<<4), usb_fs);
	asic_write(val | (en_prg<<4) | pwr, usb_fs);
}
static void platform_unconfigure_usb(void)
{
	unsigned long flags;

	spin_lock_irqsave(&usb_regs_lock, flags);
	usb_users--;
	if (usb_users == 0)
		asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap);
	spin_unlock_irqrestore(&usb_regs_lock, flags);
}
static inline void mask_asic_irq(unsigned int irq)
{
	unsigned long disable_mask;

	disable_mask = ~(1 << (irq & 0x1f));

	switch (irq >> 5) {
	case 0:
		asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0);
		break;
	case 1:
		asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1);
		break;
	case 2:
		asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2);
		break;
	case 3:
		asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3);
		break;
	default:
		BUG();
	}
}
static inline void unmask_asic_irq(unsigned int irq)
{
	unsigned long enable_bit;

	enable_bit = (1 << (irq & 0x1f));

	switch (irq >> 5) {
	case 0:
		asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0);
		break;
	case 1:
		asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1);
		break;
	case 2:
		asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2);
		break;
	case 3:
		asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3);
		break;
	default:
		BUG();
	}
}
static void platform_configure_usb(void)
{
	u32 bcm1_usb2_ctl_value;
	enum asic_type asic_type;
	unsigned long flags;

	spin_lock_irqsave(&usb_regs_lock, flags);
	usb_users++;

	if (usb_users != 1) {
		spin_unlock_irqrestore(&usb_regs_lock, flags);
		return;
	}

	asic_type = platform_get_asic();

	switch (asic_type) {
	case ASIC_ZEUS:
		fs_update(0x0000, -15, 0x02, 0, 0);
		bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
			BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
		break;

	case ASIC_CRONUS:
	case ASIC_CRONUSLITE:
		usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9);
		fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
			QAM_FS_DISABLE_DIGITAL_STANDBY);
		bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
			BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
		break;

	case ASIC_CALLIOPE:
		fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3,
			QAM_FS_DISABLE_DIGITAL_STANDBY);

		switch (platform_get_family()) {
		case FAMILY_1500VZE:
			break;

		case FAMILY_1500VZF:
			usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
				CRT_SPARE_PORT1_SHIFT_JK |
				CRT_SPARE_PORT2_FAST_EDGE |
				CRT_SPARE_PORT1_FAST_EDGE, 0);
			break;

		default:
			usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
				CRT_SPARE_PORT1_SHIFT_JK, 0);
			break;
		}

		bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
			BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
			BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
		break;

	case ASIC_GAIA:
		fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
			QAM_FS_DISABLE_DIGITAL_STANDBY);
		bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
			BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
			BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
		break;

	default:
		pr_err("Unknown ASIC type: %d\n", asic_type);
		bcm1_usb2_ctl_value = 0;
		break;
	}

	/*                   */
	asic_write(0, usb2_strap);
	/*                            */
	asic_write(bcm1_usb2_ctl_value, usb2_control);
	/*                               */
	asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc);
	/*                                */
	asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size);
	/*                                 */
	asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size);
	spin_unlock_irqrestore(&usb_regs_lock, flags);
}
Esempio n. 9
0
/*
 * \brief usb_eye_configure() for optimizing the USB eye on Calliope.
 *
 * \param     unsigned int value saved to the register.
 *
 * \return    none
 *
 */
static void __init usb_eye_configure(unsigned int value)
{
	asic_write(asic_read(crt_spare) | value, crt_spare);
}
void __init asic_irq_init(void)
{
	int i;

	/* set priority to 0 */
	write_c0_status(read_c0_status() & ~(0x0000fc00));

	asic_write(0, ien_int_0);
	asic_write(0, ien_int_1);
	asic_write(0, ien_int_2);
	asic_write(0, ien_int_3);

	asic_write(0x0fffffff, int_level_3_3);
	asic_write(0xffffffff, int_level_3_2);
	asic_write(0xffffffff, int_level_3_1);
	asic_write(0xffffffff, int_level_3_0);
	asic_write(0xffffffff, int_level_2_3);
	asic_write(0xffffffff, int_level_2_2);
	asic_write(0xffffffff, int_level_2_1);
	asic_write(0xffffffff, int_level_2_0);
	asic_write(0xffffffff, int_level_1_3);
	asic_write(0xffffffff, int_level_1_2);
	asic_write(0xffffffff, int_level_1_1);
	asic_write(0xffffffff, int_level_1_0);
	asic_write(0xffffffff, int_level_0_3);
	asic_write(0xffffffff, int_level_0_2);
	asic_write(0xffffffff, int_level_0_1);
	asic_write(0xffffffff, int_level_0_0);

	asic_write(0xf, int_int_scan);

	/*
	 * Initialize interrupt handlers.
	 */
	for (i = 0; i < NR_IRQS; i++)
		set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
}