void __init at91_add_device_usba(struct usba_platform_data *data)
{
/*
* Invalid pins are 0 on AT91, but the usba driver is shared
* with AVR32, which use negative values instead. Once/if
* gpio_is_valid() is ported to AT91, revisit this code.
*/
usba_udc_data.pdata.vbus_pin = -EINVAL;
usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
if (data && data->vbus_pin > 0) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
usba_udc_data.pdata.vbus_pin = data->vbus_pin;
}
/* Pullup pin is handled internally by USB device peripheral */
/* Clocks */
at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
platform_device_register(&at91_usba_udc_device);
}
/*
* SSC controllers are accessed through library code, instead of any
* kind of all-singing/all-dancing driver. For example one could be
* used by a particular I2S audio codec's driver, while another one
* on the same system might be used by a custom data capture driver.
*/
void __init at91_add_device_ssc(unsigned id, unsigned pins)
{
struct platform_device *pdev;
/*
* NOTE: caller is responsible for passing information matching
* "pins" to whatever will be using each particular controller.
*/
switch (id) {
case AT91SAM9G45_ID_SSC0:
pdev = &at91sam9g45_ssc0_device;
configure_ssc0_pins(pins);
at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
break;
case AT91SAM9G45_ID_SSC1:
pdev = &at91sam9g45_ssc1_device;
configure_ssc1_pins(pins);
at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
break;
default:
return;
}
platform_device_register(pdev);
}
void __init at91_add_device_usba(struct usba_platform_data *data)
{
usba_udc_data.pdata.vbus_pin = -EINVAL;
usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
if (data && data->vbus_pin > 0) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
/***
* Add by embest
* We need to disable the power for usb host, so that we could detect usb calbe plug in or plug out
* The problem is cause that usb host and usb device share a gpio pin(PD3)
*/
at91_set_gpio_output(AT91_PIN_PD3, 1);
usba_udc_data.pdata.vbus_pin = data->vbus_pin;
}
/* Pullup pin is handled internally by USB device peripheral */
/* Clocks */
at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
platform_device_register(&at91_usba_udc_device);
}
void __init at91_add_device_usba(struct usba_platform_data *data)
{
if (cpu_is_at91cap9_revB()) {
irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
AT91_MATRIX_UDPHS_BYPASS_LOCK);
}
else
at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS);
/*
* Invalid pins are 0 on AT91, but the usba driver is shared
* with AVR32, which use negative values instead. Once/if
* gpio_is_valid() is ported to AT91, revisit this code.
*/
usba_udc_data.pdata.vbus_pin = -EINVAL;
usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
if (data && data->vbus_pin > 0) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
usba_udc_data.pdata.vbus_pin = data->vbus_pin;
}
/* Pullup pin is handled internally by USB device peripheral */
/* Clocks */
at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
platform_device_register(&at91_usba_udc_device);
}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
switch (id) {
case 0: /* DBGU */
pdev = &at91cap9_dbgu_device;
configure_dbgu_pins();
at91_clock_associate("mck", &pdev->dev, "usart");
break;
case AT91CAP9_ID_US0:
pdev = &at91cap9_uart0_device;
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &pdev->dev, "usart");
break;
case AT91CAP9_ID_US1:
pdev = &at91cap9_uart1_device;
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &pdev->dev, "usart");
break;
case AT91CAP9_ID_US2:
pdev = &at91cap9_uart2_device;
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &pdev->dev, "usart");
break;
default:
return;
}
pdev->id = portnr; /* update to mapped ID */
if (portnr < ATMEL_MAX_UART)
at91_uarts[portnr] = pdev;
}
static void __init at91_add_device_tc(void)
{
/* this chip has a separate clock and irq for each TC channel */
at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
platform_device_register(&at91sam9rl_tcb_device);
}
static void __init at91_add_device_tc(void)
{
at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
platform_device_register(&at91sam9rl_tcb_device);
}
static void __init at91_add_device_tc(void)
{
/* this chip has one clock and irq for all six TC channels */
at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
platform_device_register(&at91sam9g45_tcb0_device);
at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
platform_device_register(&at91sam9g45_tcb1_device);
}
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
{
if (!data)
return;
/* input/irq */
if (data->det_pin) {
at91_set_gpio_input(data->det_pin, 1);
at91_set_deglitch(data->det_pin, 1);
}
if (data->wp_pin)
at91_set_gpio_input(data->wp_pin, 1);
if (data->vcc_pin)
at91_set_gpio_output(data->vcc_pin, 0);
if (mmc_id == 0) { /* MCI0 */
/* CLK */
at91_set_A_periph(AT91_PIN_PA2, 0);
/* CMD */
at91_set_A_periph(AT91_PIN_PA1, 1);
/* DAT0, maybe DAT1..DAT3 */
at91_set_A_periph(AT91_PIN_PA0, 1);
if (data->wire4) {
at91_set_A_periph(AT91_PIN_PA3, 1);
at91_set_A_periph(AT91_PIN_PA4, 1);
at91_set_A_periph(AT91_PIN_PA5, 1);
}
mmc0_data = *data;
at91_clock_associate("mci0_clk", &at91cap9_mmc0_device.dev, "mci_clk");
platform_device_register(&at91cap9_mmc0_device);
} else { /* MCI1 */
/* CLK */
at91_set_A_periph(AT91_PIN_PA16, 0);
/* CMD */
at91_set_A_periph(AT91_PIN_PA17, 1);
/* DAT0, maybe DAT1..DAT3 */
at91_set_A_periph(AT91_PIN_PA18, 1);
if (data->wire4) {
at91_set_A_periph(AT91_PIN_PA19, 1);
at91_set_A_periph(AT91_PIN_PA20, 1);
at91_set_A_periph(AT91_PIN_PA21, 1);
}
mmc1_data = *data;
at91_clock_associate("mci1_clk", &at91cap9_mmc1_device.dev, "mci_clk");
platform_device_register(&at91cap9_mmc1_device);
}
}
void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
{
int i;
unsigned long cs_pin;
short enable_spi0 = 0;
short enable_spi1 = 0;
/* Choose SPI chip-selects */
for (i = 0; i < nr_devices; i++) {
if (devices[i].controller_data)
cs_pin = (unsigned long) devices[i].controller_data;
else if (devices[i].bus_num == 0)
cs_pin = spi0_standard_cs[devices[i].chip_select];
else
cs_pin = spi1_standard_cs[devices[i].chip_select];
if (devices[i].bus_num == 0)
enable_spi0 = 1;
else
enable_spi1 = 1;
/* enable chip-select pin */
at91_set_gpio_output(cs_pin, 1);
/* pass chip-select pin to driver */
devices[i].controller_data = (void *) cs_pin;
}
spi_register_board_info(devices, nr_devices);
/* Configure SPI bus(es) */
if (enable_spi0) {
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk");
platform_device_register(&at91sam9260_spi0_device);
}
if (enable_spi1) {
at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk");
platform_device_register(&at91sam9260_spi1_device);
}
}
void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
{
int i;
unsigned long cs_pin;
at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
/* Enable SPI chip-selects */
for (i = 0; i < nr_devices; i++) {
if (devices[i].controller_data)
cs_pin = (unsigned long) devices[i].controller_data;
else
cs_pin = spi_standard_cs[devices[i].chip_select];
#ifdef CONFIG_SPI_AT91_MANUAL_CS
at91_set_gpio_output(cs_pin, 1);
#else
at91_set_A_periph(cs_pin, 0);
#endif
/* pass chip-select pin to driver */
devices[i].controller_data = (void *) cs_pin;
}
spi_register_board_info(devices, nr_devices);
at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi");
platform_device_register(&at91rm9200_spi_device);
}
void __init at91_init_serial(struct at91_uart_config *config)
{
int i;
/* Fill in list of supported UARTs */
for (i = 0; i < config->nr_tty; i++) {
switch (config->tty_map[i]) {
case 0:
configure_usart0_pins();
at91_uarts[i] = &at91rm9200_uart0_device;
at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart");
break;
case 1:
configure_usart1_pins();
at91_uarts[i] = &at91rm9200_uart1_device;
at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart");
break;
case 2:
configure_usart2_pins();
at91_uarts[i] = &at91rm9200_uart2_device;
at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart");
break;
case 3:
configure_usart3_pins();
at91_uarts[i] = &at91rm9200_uart3_device;
at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart");
break;
case 4:
configure_dbgu_pins();
at91_uarts[i] = &at91rm9200_dbgu_device;
at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart");
break;
default:
continue;
}
at91_uarts[i]->id = i; /* update ID number to mapped ID */
}
/* Set serial console device */
if (config->console_tty < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[config->console_tty];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_usba(struct usba_platform_data *data)
{
usba_udc_data.pdata.vbus_pin = -EINVAL;
usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
if (data && data->vbus_pin > 0) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
usba_udc_data.pdata.vbus_pin = data->vbus_pin;
}
/* Pullup pin is handled internally by USB device peripheral */
/* Clocks */
at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
platform_device_register(&at91_usba_udc_device);
}
void __init at91_add_device_ssc(unsigned id, unsigned pins)
{
struct platform_device *pdev;
switch (id) {
case AT91SAM9RL_ID_SSC0:
pdev = &at91sam9rl_ssc0_device;
configure_ssc0_pins(pins);
at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
break;
case AT91SAM9RL_ID_SSC1:
pdev = &at91sam9rl_ssc1_device;
configure_ssc1_pins(pins);
at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
break;
default:
return;
}
platform_device_register(pdev);
}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
switch (id) {
case 0:
pdev = &at91sam9rl_dbgu_device;
configure_dbgu_pins();
at91_clock_associate("mck", &pdev->dev, "usart");
break;
case AT91SAM9RL_ID_US0:
pdev = &at91sam9rl_uart0_device;
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &pdev->dev, "usart");
break;
case AT91SAM9RL_ID_US1:
pdev = &at91sam9rl_uart1_device;
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &pdev->dev, "usart");
break;
case AT91SAM9RL_ID_US2:
pdev = &at91sam9rl_uart2_device;
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &pdev->dev, "usart");
break;
case AT91SAM9RL_ID_US3:
pdev = &at91sam9rl_uart3_device;
configure_usart3_pins(pins);
at91_clock_associate("usart3_clk", &pdev->dev, "usart");
break;
default:
return;
}
pdev->id = portnr;
if (portnr < ATMEL_MAX_UART)
at91_uarts[portnr] = pdev;
}
void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
{
int i;
if (!data)
return;
/* Enable VBus control for UHP ports */
for (i = 0; i < data->ports; i++) {
if (data->vbus_pin[i])
at91_set_gpio_output(data->vbus_pin[i], 0);
}
usbh_ehci_data = *data;
at91_clock_associate("uhphs_clk", &at91_usbh_ehci_device.dev, "ehci_clk");
platform_device_register(&at91_usbh_ehci_device);
}
/* Consider only one slot : slot 0 */
void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
{
struct at_dma_slave *atslave;
if (!data)
return;
/* Must have at least one usable slot */
if (!data->slot[0].bus_width)
return;
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
atslave = kzalloc(sizeof(struct at_dma_slave), GFP_KERNEL);
/* DMA slave channel configuration */
atslave->dma_dev = &at_hdmac_device.dev;
atslave->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
atslave->cfg = ATC_FIFOCFG_HALFFIFO
| ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
if (mmc_id == 0) /* MCI0 */
atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
| ATC_DST_PER(AT_DMA_ID_MCI0);
else /* MCI1 */
atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
| ATC_DST_PER(AT_DMA_ID_MCI1);
data->dma_slave = (struct mci_dma_data *)atslave;
#endif
/* input/irq */
if (data->slot[0].detect_pin) {
at91_set_gpio_input(data->slot[0].detect_pin, 1);
at91_set_deglitch(data->slot[0].detect_pin, 1);
}
if (data->slot[0].wp_pin)
at91_set_gpio_input(data->slot[0].wp_pin, 1);
if (mmc_id == 0) { /* MCI0 */
/* CLK */
at91_set_A_periph(AT91_PIN_PA0, 0);
/* CMD */
at91_set_A_periph(AT91_PIN_PA1, 1);
/* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
at91_set_A_periph(AT91_PIN_PA2, 1);
if (data->slot[0].bus_width == 4) {
at91_set_A_periph(AT91_PIN_PA3, 1);
at91_set_A_periph(AT91_PIN_PA4, 1);
at91_set_A_periph(AT91_PIN_PA5, 1);
if (data->slot[0].bus_width == 8) {
at91_set_A_periph(AT91_PIN_PA6, 1);
at91_set_A_periph(AT91_PIN_PA7, 1);
at91_set_A_periph(AT91_PIN_PA8, 1);
at91_set_A_periph(AT91_PIN_PA9, 1);
}
}
mmc0_data = *data;
at91_clock_associate("mci0_clk", &at91sam9g45_mmc0_device.dev, "mci_clk");
platform_device_register(&at91sam9g45_mmc0_device);
} else { /* MCI1 */
/* CLK */
at91_set_A_periph(AT91_PIN_PA31, 0);
/* CMD */
at91_set_A_periph(AT91_PIN_PA22, 1);
/* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
at91_set_A_periph(AT91_PIN_PA23, 1);
if (data->slot[0].bus_width == 4) {
at91_set_A_periph(AT91_PIN_PA24, 1);
at91_set_A_periph(AT91_PIN_PA25, 1);
at91_set_A_periph(AT91_PIN_PA26, 1);
if (data->slot[0].bus_width == 8) {
at91_set_A_periph(AT91_PIN_PA27, 1);
at91_set_A_periph(AT91_PIN_PA28, 1);
at91_set_A_periph(AT91_PIN_PA29, 1);
at91_set_A_periph(AT91_PIN_PA30, 1);
}
}
mmc1_data = *data;
at91_clock_associate("mci1_clk", &at91sam9g45_mmc1_device.dev, "mci_clk");
platform_device_register(&at91sam9g45_mmc1_device);
}
}
static void __init at91_add_device_tc(void)
{
/* this chip has one clock and irq for all three TC channels */
at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk");
platform_device_register(&at91cap9_tcb_device);
}
