void board_init_f(ulong dummy) { switch_to_main_crystal_osc(); /* disable watchdog */ at91_disable_wdt(); /* PMC configuration */ at91_pmc_init(); at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); matrix_init(); redirect_int_from_saic_to_aic(); timer_init(); board_early_init_f(); preloader_console_init(); mem_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); board_init_r(NULL, 0); }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS); /* Initialize PLLA charge pump */ pmc_init_pll(AT91C_PMC_IPLLA_3); /* Switch PCK/MCK on Main clock output */ pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK); /* Switch PCK/MCK on PLLA output */ pmc_cfg_mck(BOARD_PRESCALER_PLLA); /* Initialize timer */ timer_init(); /* Initialize the DBGU */ initialize_dbgu(); #if defined(CONFIG_LPDDR2) lpddr2_init(); #endif /* Initialize 1-Wire */ one_wire_hw_init(); /* Reset HDMI SiI9022 */ SiI9022_hw_reset(); }
void board_init_f(ulong dummy) { lowlevel_clock_init(); #if !defined(CONFIG_WDT_AT91) at91_disable_wdt(); #endif /* * At this stage the main oscillator is supposed to be enabled * PCK = MCK = MOSC */ at91_pllicpr_init(0x00); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ at91_plla_init(CONFIG_SYS_AT91_PLLA); /* PCK = PLLA = 2 * MCK */ at91_mck_init(CONFIG_SYS_MCKR); /* Switch MCK on PLLA output */ at91_mck_init(CONFIG_SYS_MCKR_CSS); #if defined(CONFIG_SYS_AT91_PLLB) /* Configure PLLB */ at91_pllb_init(CONFIG_SYS_AT91_PLLB); #endif /* Enable External Reset */ enable_ext_reset(); /* Initialize matrix */ matrix_init(); gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; /* * init timer long enough for using in spl. */ timer_init(); /* enable clocks for all PIOs */ #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) at91_periph_clk_enable(ATMEL_ID_PIOAB); at91_periph_clk_enable(ATMEL_ID_PIOCD); #else at91_periph_clk_enable(ATMEL_ID_PIOA); at91_periph_clk_enable(ATMEL_ID_PIOB); at91_periph_clk_enable(ATMEL_ID_PIOC); #endif #if defined(CONFIG_SPL_SERIAL_SUPPORT) /* init console */ at91_seriald_hw_init(); preloader_console_init(); #endif mem_init(); at91_spl_board_init(); }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* At this stage the main oscillator is supposed * to be enabled PCK = MCK = MOSC */ /* Switch PCK/MCK on Main clock output */ pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS); /* Initialize PLLA charge pump */ /* not needed for SAMA5D4 */ pmc_init_pll(0); /* Switch MCK on PLLA output */ pmc_cfg_mck(BOARD_PRESCALER_PLLA); /* Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); #if defined(CONFIG_ENTER_NWD) cpacr_init(); /* Program the DACR to allow client access to *all* domains */ dacr_swd_init(); #endif #if defined(CONFIG_MATRIX) /* Initialize the matrix */ matrix_init(); #endif /* initialize the dbgu */ initialize_dbgu(); #if defined(CONFIG_MATRIX) matrix_read_slave_security(); matrix_read_periperal_security(); #endif /* Init timer */ timer_init(); #ifdef CONFIG_DDR2 /* Initialize MPDDR Controller */ ddramc_init(); #endif /* Prepare L2 cache setup */ l2cache_prepare(); }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* * while coming from the ROM code, we run on PLLA @ 396 MHz / 132 MHz * so we need to slow down and configure MCKR accordingly. * This is why we have a special flavor of the switching function. */ /* Switch PCK/MCK on Main Clock output */ pmc_cfg_mck_down(BOARD_PRESCALER_MAIN_CLOCK); /* Configure PLLA */ pmc_cfg_plla(PLLA_SETTINGS); /* Initialize PLLA charge pump */ /* No need: we keep what is set in ROM code */ //pmc_init_pll(0x3); /* Switch MCK on PLLA output */ pmc_cfg_mck(BOARD_PRESCALER_PLLA); /* Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); #if defined(CONFIG_MATRIX) /* Initialize the matrix */ matrix_init(); #endif /* initialize the dbgu */ initialize_dbgu(); /* Init timer */ timer_init(); #if defined(CONFIG_DDR3) /* Initialize MPDDR Controller */ ddramc_init(); #elif defined(CONFIG_LPDDR1) lpddr1_init(); #elif defined(CONFIG_LPDDR2) lpddr2_init(); #elif defined(CONFIG_LPDDR3) lpddr3_init(); #endif /* Prepare L2 cache setup */ l2cache_prepare(); at91_init_can_message_ram(); }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* * At this stage the main oscillator is supposed to be enabled * PCK = MCK = MOSC */ pmc_init_pll(0); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); /* PCK = PLLA/2 = 3 * MCK */ pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT); /* Switch MCK on PLLA output */ pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT); /* Configure PLLB */ //pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT); /* Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); /* Configure the EBI Slave Slot Cycle to 64 */ writel((readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40, (AT91C_BASE_MATRIX + MATRIX_SCFG3)); /* Init timer */ timer_init(); /* Initialize dbgu */ initialize_dbgu(); #ifdef CONFIG_SDRAM /* Initlialize sdram controller */ sdramc_init(); #endif #ifdef CONFIG_USER_HW_INIT hw_init_hook(); #endif #if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY) /* Init the recovery buttons pins */ recovery_buttons_hw_init(); #endif }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* * At this stage the main oscillator * is supposed to be enabled PCK = MCK = MOSC */ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS); /* Initialize PLLA charge pump */ pmc_init_pll(AT91C_PMC_IPLLA_3); /* Switch PCK/MCK on Main clock output */ pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK); /* Switch PCK/MCK on PLLA output */ pmc_cfg_mck(BOARD_PRESCALER_PLLA); #ifdef CONFIG_USER_HW_INIT /* Set GMAC & EMAC pins to output low */ at91_special_pio_output_low(); #endif /* Init timer */ timer_init(); #ifdef CONFIG_SCLK slowclk_enable_osc32(); #endif /* initialize the dbgu */ initialize_dbgu(); #ifdef CONFIG_DDR2 /* Initialize MPDDR Controller */ ddramc_init(); #endif #ifdef CONFIG_PM_EXTERNAL_DEVICES #ifdef CONFIG_MACB /* Make PHYs to power down mode */ phys_enter_power_down(); #endif /* #ifdef CONFIG_MACB */ #endif /* #ifdef CONFIG_PM_EXTERNAL_DEVICES */ }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* * At this stage the main oscillator is supposed to be enabled * PCK = MCK = MOSC */ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); /* PCK = PLLA = 2 * MCK */ pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT); /* Switch MCK on PLLA output */ pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT); /* Configure PLLB */ //pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT); /* Enable External Reset */ writel(((0xA5 << 24) | AT91C_RSTC_URSTEN), AT91C_BASE_RSTC + RSTC_RMR); /* Initialize matrix */ at91_matrix_hw_init(); /* Init timer */ timer_init(); /* Initialize dbgu */ initialize_dbgu(); #ifdef CONFIG_SDRAM /* Initlialize sdram controller */ sdramc_init(); #endif #ifdef CONFIG_USER_HW_INIT hw_init_hook(); #endif #if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY) /* Init the recovery buttons pins */ recovery_buttons_hw_init(); #endif }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* At this stage the main oscillator * is supposed to be enabled PCK = MCK = MOSC */ writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); /* PCK = PLLA/2 = 3 * MCK */ pmc_cfg_mck(BOARD_PRESCALER, PLL_LOCK_TIMEOUT); /* Switch MCK on PLLA output */ pmc_cfg_mck(0x1302, PLL_LOCK_TIMEOUT); /* Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); /* Init timer */ timer_init(); #ifdef CONFIG_SCLK slowclk_enable_osc32(); #endif /* Initialize dbgu */ initialize_dbgu(); #ifdef CONFIG_DDR2 /* Initialize DDRAM Controller */ ddramc_init(); #endif #ifdef CONFIG_USER_HW_INIT hw_init_hook(); #endif #if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY) /* Init the recovery buttons pins */ recovery_buttons_hw_init(); #endif /* do some special init */ ek_special_hw_init(); }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* At this stage the main oscillator is supposed to be enabled PCK = MCK = MOSC */ writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); /* PCK = PLLA/2 = 3 * MCK */ pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT); /* Switch MCK on PLLA output */ pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT); /* Enable External Reset */ writel(((0xA5 << 24) | AT91C_RSTC_URSTEN), AT91C_BASE_RSTC + RSTC_RMR); /* Init timer */ timer_init(); #ifdef CONFIG_SCLK slowclk_enable_osc32(); #endif /* initialize the dbgu */ initialize_dbgu(); #ifdef CONFIG_DDR2 /* Initialize MPDDR Controller */ ddramc_init(); #endif /* load one wire information */ one_wire_hw_init(); #ifdef CONFIG_USER_HW_INIT hw_init_hook(); #endif HDMI_Qt1070_workaround(); #if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY) /* Init the recovery buttons pins */ recovery_buttons_hw_init(); #endif }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* * At this stage the main oscillator is * supposed to be enabled PCK = MCK = MOSC */ pmc_init_pll(0); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS); /* Switch PCK/MCK on Main clock output */ pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK); /* Switch PCK/MCK on PLLA output */ pmc_cfg_mck(BOARD_PRESCALER_PLLA); /* Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); /* Init timer */ timer_init(); #ifdef CONFIG_SCLK slowclk_enable_osc32(); #endif /* Initialize dbgu */ initialize_dbgu(); #ifdef CONFIG_DDR2 /* Initialize DDRAM Controller */ ddramc_init(); #endif /* one wire pin init */ one_wire_hw_init(); #ifdef CONFIG_USER_HW_INIT hw_init_hook(); #endif }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* * At this stage the main oscillator is supposed to be enabled * PCK = MCK = MOSC */ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS); /* PCK = PLLA = 2 * MCK */ pmc_cfg_mck(MCKR_SETTINGS); /* Switch MCK on PLLA output */ pmc_cfg_mck(MCKR_CSS_SETTINGS); /* Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); at91_matrix_hw_init(); /* Init timer */ timer_init(); /* Initialize dbgu */ initialize_dbgu(); #ifdef CONFIG_SDRAM /* Initialize SDRAMC0 */ sdramc0_init(); #endif #if defined(CONFIG_PSRAM) psram_hw_init(); #endif #if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY) /* Init the recovery buttons pins */ recovery_buttons_hw_init(); #endif }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* At this stage the main oscillator is *supposed to be enabled PCK = MCK = MOSC */ writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); /* PCK = PLLA/2 = 3 * MCK */ pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT); /* Switch MCK on PLLA output */ pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT); /*Enable External Reset */ writel(((0xA5 << 24) | AT91C_RSTC_URSTEN), AT91C_BASE_RSTC + RSTC_RMR); /* Init timer */ timer_init(); #ifdef CONFIG_SCLK slowclk_enable_osc32(); #endif /* Initialize dbgu */ initialize_dbgu(); #ifdef CONFIG_DDR2 /* Initialize DDRAM Controller */ ddramc_init(); #endif /* one wire pin init */ one_wire_hw_init(); #ifdef CONFIG_USER_HW_INIT hw_init_hook(); #endif }
void s_init(void) { switch_to_main_crystal_osc(); /* disable watchdog */ at91_disable_wdt(); /* PMC configuration */ at91_pmc_init(); at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); timer_init(); board_early_init_f(); preloader_console_init(); mem_init(); }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* * while coming from the ROM code, we run on PLLA @ 396 MHz / 132 MHz * so we need to slow down and configure MCKR accordingly. * This is why we have a special flavor of the switching function. */ /* Switch PCK/MCK clock source to the main clock */ pmc_cfg_mck_down(BOARD_PRESCALER_MAIN_CLOCK); /* Configure PLLA */ pmc_cfg_plla(PLLA_SETTINGS); /* Switch MCK clock source to PLLA */ pmc_cfg_mck(BOARD_PRESCALER_PLLA); /* Enable external reset */ writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); #if defined(CONFIG_MATRIX) /* Initialize the matrix */ matrix_init(); #endif /* initialize the dbgu */ initialize_dbgu(); /* Init timer */ timer_init(); #if defined(CONFIG_DDR3) /* Initialize MPDDR Controller */ ddramc_init(); #endif /* Prepare L2 cache setup */ l2cache_prepare(); }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* * At this stage the main oscillator * is supposed to be enabled PCK = MCK = MOSC */ pmc_init_pll(0); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS); /* Switch PCK/MCK on Main clock output */ pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK); /* Switch PCK/MCK on PLLA output */ pmc_cfg_mck(BOARD_PRESCALER_PLLA); /* Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); /* Init timer */ timer_init(); /* Initialize dbgu */ initialize_dbgu(); #ifdef CONFIG_DDR2 /* Initialize DDRAM Controller */ ddramc_init(); #endif #if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY) /* Init the recovery buttons pins */ recovery_buttons_hw_init(); #endif /* do some special init */ ek_special_hw_init(); }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* Adjust waitstates to access internal flash */ writel(AT91C_EEFC_FWS_6WS, AT91C_BASE_EEFC + EEFC_FMR); /* * At this stage the main oscillator is supposed to be enabled * PCK = MCK = MOSC */ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); /* PCK = PLLA = 2 * MCK */ pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT); /* Switch MCK on PLLA output */ pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT); /* Configure PLLB */ //pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT); /* Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); #ifdef CONFIG_DEBUG /* Initialize dbgu */ initialize_dbgu(); #endif #ifdef CONFIG_SDRAM /* Configure SDRAM Controller */ sdramc_init(); #endif #ifdef CONFIG_USER_HW_INIT hw_init_hook(); #endif }
void board_init_f(ulong dummy) { int ret; switch_to_main_crystal_osc(); #ifdef CONFIG_SAMA5D2 configure_2nd_sram_as_l2_cache(); #endif /* disable watchdog */ at91_disable_wdt(); /* PMC configuration */ at91_pmc_init(); at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); matrix_init(); redirect_int_from_saic_to_aic(); timer_init(); board_early_init_f(); mem_init(); ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); hang(); } preloader_console_init(); }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* * At this stage the main oscillator * is supposed to be enabled PCK = MCK = MOSC */ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); /* Initialize PLLA charge pump */ pmc_init_pll(AT91C_PMC_IPLLA_3); /* Switch PCK/MCK on Main clock output */ pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT); /* Switch PCK/MCK on PLLA output */ pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT); #ifdef CONFIG_USER_HW_INIT /* Set GMAC & EMAC pins to output low */ at91_special_pio_output_low(); #endif /* Disable the software modem clock */ at91_disable_smd_clock(); /* Init timer */ timer_init(); #ifdef CONFIG_SCLK slowclk_enable_osc32(); #endif /* initialize the dbgu */ initialize_dbgu(); #ifdef CONFIG_DDR2 /* Initialize MPDDR Controller */ ddramc_init(); #endif #ifdef CONFIG_TWI twi_init(); #endif #ifdef CONFIG_ACT8865 /* Set ACT8865 REG power saving mode */ act8865_set_power_saving_mode(); /* Set ACT8865 output voltage */ sama5d4ek_act8865_set_reg_voltage(); /* Dsiable ACT8865 I2C interface */ if (act8865_workaround_disable_i2c()) while (1) ; #endif #ifdef CONFIG_PM_EXTERNAL_DEVICES #ifdef CONFIG_MACB /* Make PHYs to power down mode */ phys_enter_power_down(); #endif #endif /* #ifdef CONFIG_PM_EXTERNAL_DEVICES */ }
void hw_init(void) { /* Disable watchdog */ at91_disable_wdt(); /* At this stage the main oscillator is supposed * to be enabled PCK = MCK = MOSC */ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); /* Initialize PLLA charge pump */ /* not needed for SAMA5D4 */ pmc_init_pll(0); /* Switch MCK on PLLA output */ pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT); /* Setup AHB 32-bit Matrix Divisor */ pmc_cfg_h32mxdiv(BOARD_H32MX, PLL_LOCK_TIMEOUT); /* Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); #if defined(CONFIG_ENTER_NWD) cpacr_init(); /* Program the DACR to allow client access to *all* domains */ dacr_swd_init(); #endif #if defined(CONFIG_MATRIX) /* Initialize the matrix */ matrix_init(); #endif /* initialize the dbgu */ initialize_dbgu(); /* Redirect all interrupts to non-secure AIC */ redirect_interrupts_to_aic(); #if defined(CONFIG_MATRIX) matrix_read_slave_security(); matrix_read_periperal_security(); #endif /* Init timer */ timer_init(); #ifdef CONFIG_DDR2 /* Initialize MPDDR Controller */ ddramc_init(); #endif /* load one wire information */ one_wire_hw_init(); /* Reset HDMI SiI9022 */ SiI9022_hw_reset(); /* Disable software modem device's clock */ at91_disable_smd_clock(); #ifdef CONFIG_TWI twi_init(); #endif #ifdef CONFIG_ACT8865 /* Set ACT8865 REG power saving mode */ act8865_set_power_saving_mode(); /* Set ACT8865 output voltage */ sama5d4ek_act8865_set_reg_voltage(); /* Dsiable ACT8865 I2C interface */ if (act8865_workaround_disable_i2c()) while (1) ; #endif #ifdef CONFIG_PM_EXTERNAL_DEVICES #ifdef CONFIG_HDMI SiI9022_enter_power_state_D3_Cold(); #endif #ifdef CONFIG_WM8904 wm8904_enter_low_power(); #endif #ifdef CONFIG_MACB /* Make PHYs to power down mode */ phys_enter_power_down(); #endif #endif /* #ifdef CONFIG_PM_EXTERNAL_DEVICES */ #ifdef CONFIG_USER_HW_INIT hw_init_hook(); #endif }