void board_init_f(ulong dummy)
{
lowlevel_clock_init();
#if !defined(CONFIG_WDT_AT91)
at91_disable_wdt();
#endif
/*
* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC
*/
at91_pllicpr_init(0x00);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
at91_plla_init(CONFIG_SYS_AT91_PLLA);
/* PCK = PLLA = 2 * MCK */
at91_mck_init(CONFIG_SYS_MCKR);
/* Switch MCK on PLLA output */
at91_mck_init(CONFIG_SYS_MCKR_CSS);
#if defined(CONFIG_SYS_AT91_PLLB)
/* Configure PLLB */
at91_pllb_init(CONFIG_SYS_AT91_PLLB);
#endif
/* Enable External Reset */
enable_ext_reset();
/* Initialize matrix */
matrix_init();
gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
/*
* init timer long enough for using in spl.
*/
timer_init();
/* enable clocks for all PIOs */
#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
at91_periph_clk_enable(ATMEL_ID_PIOAB);
at91_periph_clk_enable(ATMEL_ID_PIOCD);
#else
at91_periph_clk_enable(ATMEL_ID_PIOA);
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_periph_clk_enable(ATMEL_ID_PIOC);
#endif
#if defined(CONFIG_SPL_SERIAL_SUPPORT)
/* init console */
at91_seriald_hw_init();
preloader_console_init();
#endif
mem_init();
at91_spl_board_init();
}
int board_early_init_f(void)
{
at91_periph_clk_enable(ATMEL_ID_PIOAB);
at91_periph_clk_enable(ATMEL_ID_PIOCD);
at91_seriald_hw_init();
return 0;
}
int board_early_init_f(void)
{
at91_periph_clk_enable(ATMEL_ID_PIOA);
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_periph_clk_enable(ATMEL_ID_PIOC);
at91_periph_clk_enable(ATMEL_ID_PIOD);
board_uart1_hw_init();
return 0;
}
int board_early_init_f(void)
{
at91_periph_clk_enable(ATMEL_ID_PIOA);
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_periph_clk_enable(ATMEL_ID_PIOC);
at91_periph_clk_enable(ATMEL_ID_PIOD);
at91_periph_clk_enable(ATMEL_ID_PIOE);
vinco_serial3_hw_init();
return 0;
}
void at91_can_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */
at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */
at91_periph_clk_enable(ATMEL_ID_CAN);
}
void at91_seriald_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
at91_periph_clk_enable(ATMEL_ID_SYS);
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
at91_periph_clk_enable(ATMEL_ID_SPI1);
if (cs_mask & (1 << 0))
at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
if (cs_mask & (1 << 1))
at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
if (cs_mask & (1 << 2))
at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
if (cs_mask & (1 << 3))
at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
if (cs_mask & (1 << 4))
at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
if (cs_mask & (1 << 5))
at91_set_pio_output(AT91_PIO_PORTA, 0, 0);
if (cs_mask & (1 << 6))
at91_set_pio_output(AT91_PIO_PORTA, 31, 0);
if (cs_mask & (1 << 7))
at91_set_pio_output(AT91_PIO_PORTA, 30, 0);
}
static void board_uart1_hw_init(void)
{
atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */
atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
at91_periph_clk_enable(ATMEL_ID_UART1);
}
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_SPI0);
if (cs_mask & (1 << 0))
at91_set_a_periph(AT91_PIO_PORTD, 13, 0);
if (cs_mask & (1 << 1))
at91_set_b_periph(AT91_PIO_PORTD, 14, 0);
if (cs_mask & (1 << 2))
at91_set_b_periph(AT91_PIO_PORTD, 15, 0);
if (cs_mask & (1 << 3))
at91_set_b_periph(AT91_PIO_PORTD, 16, 0);
if (cs_mask & (1 << 4))
at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
if (cs_mask & (1 << 5))
at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
if (cs_mask & (1 << 6))
at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
if (cs_mask & (1 << 7))
at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
}
static void sama5d4ek_lcd_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_LCDC);
}
void at91_lcd_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
/* The lower 16-bit of LCD only available on Port A */
at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */
at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_LCDC);
}
static void ma5d4evk_serial_hw_init(void)
{
/* USART0 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */
at91_periph_clk_enable(ATMEL_ID_USART0);
/* USART1 */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */
at91_periph_clk_enable(ATMEL_ID_USART1);
}
void mem_init(void)
{
struct atmel_mpddrc_config ddr2;
const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
u32 tmp;
ddr2_conf(&ddr2);
/* Enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
at91_system_clk_enable(AT91_PMC_DDR);
tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE;
writel(tmp, &mpddr->rd_data_path);
tmp = readl(&mpddr->io_calibr);
tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV |
ATMEL_MPDDRC_IO_CALIBR_TZQIO |
ATMEL_MPDDRC_IO_CALIBR_CALCODEP |
ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) |
ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 |
ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) |
ATMEL_MPDDRC_IO_CALIBR_EN_CALIB;
writel(tmp, &mpddr->io_calibr);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
}
static void board_uart0_hw_init(void)
{
atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
at91_periph_clk_enable(ATMEL_ID_UART0);
}
static void corvus_macb_hw_init(void)
{
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_EMAC);
/*
* Disable pull-up on:
* RXDV (PA15) => PHY normal mode (not Test mode)
* ERX0 (PA12) => PHY ADDR0
* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
at91_phy_reset();
/* Re-enable pull-up */
at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
/* And the pins. */
at91_macb_hw_init();
}
void sama5d3_xplained_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
at91_periph_clk_enable(ATMEL_ID_SMC);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
&smc->cs[3].cycle);
writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_MODE_DBW_8 |
#endif
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
}
void sama5d4_xplained_mci1_hw_init(void)
{
at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
* external pull up, the pull up resistor will be very small, if so
* the power consumption will increase, so disable the interanl pull
* down to save the power.
*/
at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI1);
}
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
struct atmel_mpddrc_config ddrc_config;
u32 reg;
ddrc_conf(&ddrc_config);
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
writel(AT91_PMC_DDR, &pmc->scer);
reg = readl(&mpddrc->io_calibr);
reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
writel(reg, &mpddrc->io_calibr);
writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
&mpddrc->rd_data_path);
ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
writel(0x3, &mpddrc->cal_mr4);
writel(64, &mpddrc->tim_cal);
}
void at91_mci_hw_init(void)
{
at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */
at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */
at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */
at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */
at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */
#ifdef CONFIG_ATMEL_MCI_8BIT
at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */
at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */
at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */
at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */
#endif
at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI0);
/* Pin muxing for MCI1 */
at91_set_pio_output(AT91_PIO_PORTB, 12, 0); /* MCI1 Power */
at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* MCI1 CMD */
at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* MCI1 DA0 */
at91_set_a_periph(AT91_PIO_PORTB, 21, 0); /* MCI1 DA1 */
at91_set_a_periph(AT91_PIO_PORTB, 22, 0); /* MCI1 DA2 */
at91_set_a_periph(AT91_PIO_PORTB, 23, 0); /* MCI1 DA3 */
at91_set_a_periph(AT91_PIO_PORTB, 24, 0); /* MCI1 CLK */
}
void at91_serial2_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
at91_periph_clk_enable(ATMEL_ID_USART2);
}
void vinco_mci0_hw_init(void)
{
at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */
at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */
at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */
at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */
at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */
at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */
at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */
at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */
at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */
at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */
/*
* As the mci io internal pull down is too strong, so if the io needs
* external pull up, the pull up resistor will be very small, if so
* the power consumption will increase, so disable the interanl pull
* down to save the power.
*/
at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_MCI0);
}
static void picosam9g45_macb_hw_init(void)
{
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
at91_periph_clk_enable(ATMEL_ID_EMAC);
/*
* Disable pull-up on:
* RXDV (PA15) => PHY normal mode (not Test mode)
* ERX0 (PA12) => PHY ADDR0
* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
writel(pin_to_mask(AT91_PIN_PA15) |
pin_to_mask(AT91_PIN_PA12) |
pin_to_mask(AT91_PIN_PA13),
&pioa->pudr);
at91_phy_reset();
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PA15) |
pin_to_mask(AT91_PIN_PA12) |
pin_to_mask(AT91_PIN_PA13),
&pioa->puer);
/* And the pins. */
at91_macb_hw_init();
}
static void at91sam9g45_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
at91_periph_clk_enable(ATMEL_ID_LCDC);
}
static void picosam9g45_usb_hw_init(void)
{
at91_periph_clk_enable(ATMEL_ID_PIODE);
at91_set_gpio_output(AT91_PIN_PD1, 0);
at91_set_gpio_output(AT91_PIN_PD3, 0);
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */
at91_periph_clk_enable(ATMEL_ID_SPI1);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_b_periph(AT91_PIO_PORTC, 3, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
}
}
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
at91_periph_clk_enable(ATMEL_ID_SPI0);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
}
}
void at91_macb_hw_init(void)
{
if (has_emac0()) {
at91_periph_clk_enable(ATMEL_ID_EMAC0);
/* EMAC0 pins setup */
at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
}
if (has_emac1()) {
at91_periph_clk_enable(ATMEL_ID_EMAC1);
/* EMAC1 pins setup */
at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
}
#ifndef CONFIG_RMII
/* Only emac0 support MII */
if (has_emac0()) {
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
}
#endif
}
static void vinco_serial3_hw_init(void)
{
at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART3);
}
void at91_serial0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTD, 17, PUP); /* RXD0 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART0);
}
void at91_serial1_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTB, 29, PUP); /* RXD1 */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_USART1);
}
