static void __init pb44_init(void)
{
i2c_register_board_info(0, pb44_i2c_board_info,
ARRAY_SIZE(pb44_i2c_board_info));
platform_device_register(&pb44_i2c_gpio_device);
ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio),
pb44_leds_gpio);
ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL,
ARRAY_SIZE(pb44_gpio_keys),
pb44_gpio_keys);
ath79_register_spi(&pb44_spi_data, pb44_spi_info,
ARRAY_SIZE(pb44_spi_info));
ath79_register_usb();
ath79_register_pci();
}
static void __init tl_wr1043nd_v2_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&wr1043nd_v2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043_v2_leds_gpio),
tl_wr1043_v2_leds_gpio);
ath79_register_gpio_keys_polled(-1, TL_WR1043_V2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr1043_v2_gpio_keys),
tl_wr1043_v2_gpio_keys);
ath79_init_mac(tmpmac, mac, -1);
ath79_register_wmac(art + TL_WR1043_V2_WMAC_CALDATA_OFFSET, tmpmac);
mdiobus_register_board_info(wr1043nd_v2_mdio0_info,
ARRAY_SIZE(wr1043nd_v2_mdio0_info));
ath79_register_mdio(0, 0x0);
wr1043nd_v2_gmac_setup();
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
ath79_register_usb();
gpio_request_one(TL_WR1043_V2_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
}
static void __init dir825c1_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
dir825c1_read_ascii_mac(mac1, mac + DIR825C1_MAC0_OFFSET);
dir825c1_read_ascii_mac(mac2, mac + DIR825C1_MAC1_OFFSET);
ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio),
dir825c1_leds_gpio);
ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir825c1_gpio_keys),
dir825c1_gpio_keys);
ap9x_pci_setup_wmac_led_pin(0, 13);
ap9x_pci_setup_wmac_led_pin(1, 32);
ath79_init_mac(tmpmac, mac1, 0);
ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, tmpmac);
ath79_init_mac(tmpmac, mac2, 0);
ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(dir825c1_mdio0_info,
ARRAY_SIZE(dir825c1_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_register_usb();
}
static void __init wdr4300_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&wdr4300_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr4300_leds_gpio),
wdr4300_leds_gpio);
ath79_register_gpio_keys_polled(-1, WDR4300_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wdr4300_gpio_keys),
wdr4300_gpio_keys);
ath79_wmac_set_ext_lna_gpio(0, WDR4300_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, WDR4300_GPIO_EXTERNAL_LNA1);
ath79_init_mac(tmpmac, mac, -1);
ath79_register_wmac(art + WDR4300_WMAC_CALDATA_OFFSET, tmpmac);
ath79_init_mac(tmpmac, mac, 0);
ap9x_pci_setup_wmac_led_pin(0, 0);
ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(wdr4300_mdio0_info,
ARRAY_SIZE(wdr4300_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -2);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
gpio_request_one(WDR4300_GPIO_USB1_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB1 power");
gpio_request_one(WDR4300_GPIO_USB2_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB2 power");
ath79_register_usb();
}
static void __init wzrhpag300h_setup(void)
{
u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1f051000);
u8 *eeprom2 = (u8 *) KSEG1ADDR(0x1f055000);
u8 *mac1 = eeprom1 + WZRHPAG300H_MAC_OFFSET;
u8 *mac2 = eeprom2 + WZRHPAG300H_MAC_OFFSET;
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 1);
ath79_register_mdio(0, ~(BIT(0) | BIT(4)));
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = BIT(4);
ath79_register_eth(0);
ath79_register_eth(1);
gpio_request_one(2, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpag300h_leds_gpio),
wzrhpag300h_leds_gpio);
ath79_register_gpio_keys_polled(-1, WZRHPAG300H_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wzrhpag300h_gpio_keys),
wzrhpag300h_gpio_keys);
ath79_register_m25p80_multi(&wzrhpag300h_flash_data);
ap94_pci_init(eeprom1, mac1, eeprom2, mac2);
ap9x_pci_setup_wmac_led_pin(0, 1);
ap9x_pci_setup_wmac_led_pin(1, 5);
ap9x_pci_setup_wmac_leds(0, wzrhpag300h_wmac0_leds_gpio,
ARRAY_SIZE(wzrhpag300h_wmac0_leds_gpio));
ap9x_pci_setup_wmac_leds(1, wzrhpag300h_wmac1_leds_gpio,
ARRAY_SIZE(wzrhpag300h_wmac1_leds_gpio));
}
static void __init carambola2_setup(void)
{
carambola2_common_setup();
ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
ath79_register_leds_gpio(-1, ARRAY_SIZE(carambola2_leds_gpio),
carambola2_leds_gpio);
ath79_register_gpio_keys_polled(-1, CARAMBOLA2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(carambola2_gpio_keys),
carambola2_gpio_keys);
ath79_register_usb();
}
static void __init tl_wr842n_v2_setup(void)
{
tl_ap123_setup();
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio),
tl_wr841n_v8_leds_gpio);
ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr841n_v8_gpio_keys),
tl_wr841n_v8_gpio_keys);
gpio_request_one(TL_MR3420V2_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
}
static void __init dw33d_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dw33d_leds_gpio),
dw33d_leds_gpio);
ath79_register_gpio_keys_polled(-1, DW33D_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dw33d_gpio_keys),
dw33d_gpio_keys);
ath79_register_usb();
ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
ath79_register_nfc();
ath79_register_pci();
ath79_register_wmac(art + DW33D_WMAC_CALDATA_OFFSET, art + DW33D_WMAC_OFFSET);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + DW33D_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + DW33D_MAC1_OFFSET, 0);
mdiobus_register_board_info(dw33d_mdio0_info,
ARRAY_SIZE(dw33d_mdio0_info));
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_register_eth(0);
/* GMAC1 is connected tot eh SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_register_eth(1);
}
static void __init cf_exxxn_common_setup(unsigned long art_ofs, int gpio_wdt)
{
u8 *art = (u8 *) KSEG1ADDR(0x1f001000 + art_ofs);
if (gpio_wdt > -1) {
gpio_request_one(gpio_wdt, GPIOF_OUT_INIT_HIGH,
"PT7A7514 watchdog");
setup_timer(&gpio_wdt_timer, gpio_wdt_toggle, gpio_wdt);
gpio_wdt_toggle(gpio_wdt);
}
ath79_register_m25p80(NULL);
ath79_register_wmac(art, NULL);
ath79_register_usb();
}
static void __init mynet_n750_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n750_leds_gpio),
mynet_n750_leds_gpio);
ath79_register_gpio_keys_polled(-1, MYNET_N750_KEYS_POLL_INTERVAL,
ARRAY_SIZE(mynet_n750_gpio_keys),
mynet_n750_gpio_keys);
/*
* Control signal for external LNAs 0 and 1
* Taken from GPL bootloader source:
* board/ar7240/db12x/alpha_gpio.c
*/
ath79_wmac_set_ext_lna_gpio(0, MYNET_N750_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, MYNET_N750_GPIO_EXTERNAL_LNA1);
mynet_n750_get_mac("wlan24mac=", tmpmac);
ath79_register_wmac(art + MYNET_N750_WMAC_CALDATA_OFFSET, tmpmac);
mynet_n750_get_mac("wlan5mac=", tmpmac);
ap91_pci_init(art + MYNET_N750_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(mynet_n750_mdio0_info,
ARRAY_SIZE(mynet_n750_mdio0_info));
ath79_mdio0_data.reset = mynet_n750_mdio_fixup;
ath79_register_mdio(0, 0x0);
mynet_n750_get_mac("lanmac=", ath79_eth0_data.mac_addr);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_register_usb();
}
static void __init dir825b1_setup(void)
{
u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
dir825b1_read_ascii_mac(mac1, DIR825B1_MAC_LOCATION_0);
dir825b1_read_ascii_mac(mac2, DIR825B1_MAC_LOCATION_1);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 2);
ath79_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_pll_data.pll_1000 = 0x11110000;
ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 3);
ath79_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = 0x10;
ath79_eth1_pll_data.pll_1000 = 0x11110000;
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_m25p80(&dir825b1_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio),
dir825b1_leds_gpio);
ath79_register_gpio_keys_polled(-1, DIR825B1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir825b1_gpio_keys),
dir825b1_gpio_keys);
ath79_register_usb();
platform_device_register(&dir825b1_rtl8366s_device);
ap9x_pci_setup_wmac_led_pin(0, 5);
ap9x_pci_setup_wmac_led_pin(1, 5);
ap94_pci_init((u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0), mac1,
(u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1), mac2);
}
static void __init wpj344_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj344_leds_gpio),
wpj344_leds_gpio);
ath79_register_gpio_keys_polled(-1, WPJ344_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wpj344_gpio_keys),
wpj344_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + WPJ344_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(wpj344_mdio0_info,
ARRAY_SIZE(wpj344_mdio0_info));
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ344_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ344_MAC1_OFFSET, 0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
ath79_register_eth(1);
}
/*
* Common peripherals init routine for all SPI NOR devices.
* Sets SPI and USB.
*/
static void __init rbspi_peripherals_setup(u32 flags)
{
unsigned spi_n;
if (flags & RBSPI_HAS_SSR)
spi_n = ARRAY_SIZE(rbspi_spi_info);
else
spi_n = 1; /* only one device on bus0 */
rbspi_ath79_spi_data.num_chipselect = spi_n;
rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios;
ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n);
if (flags & RBSPI_HAS_USB)
ath79_register_usb();
if (flags & RBSPI_HAS_PCI)
ath79_register_pci();
}
static void __init ds_setup(void)
{
u32 t;
ds_common_setup();
ath79_register_leds_gpio(-1, ARRAY_SIZE(ds_leds_gpio),
ds_leds_gpio);
ath79_register_usb();
//Disable the Function for some pins to have GPIO functionality active
// GPIO6-7-8 and GPIO11
ath79_gpio_function_setup(AR933X_GPIO_FUNC_JTAG_DISABLE | AR933X_GPIO_FUNC_I2S_MCK_EN, 0);
ath79_gpio_function2_setup(AR933X_GPIO_FUNC2_JUMPSTART_DISABLE, 0);
printk("Setting DogStick2 GPIO\n");
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
// Put the avr reset to high
if (gpio_request_one(DS_GPIO_AVR_RESET_DS2,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, "OE-1") != 0)
printk("Error setting GPIO OE\n");
gpio_unexport(DS_GPIO_AVR_RESET_DS2);
gpio_free(DS_GPIO_AVR_RESET_DS2);
// enable OE of level shifter
if (gpio_request_one(DS_GPIO_OE,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, "OE-1") != 0)
printk("Error setting GPIO OE\n");
if (gpio_request_one(DS_GPIO_UART_ENA,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, "UART-ENA") != 0)
printk("Error setting GPIO Uart Enable\n");
// enable OE of level shifter
if (gpio_request_one(DS_GPIO_OE2,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, "OE-2") != 0)
printk("Error setting GPIO OE2\n");
}
static void __init gl_ar300m_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_register_spi(&gl_ar300m_spi_data, gl_ar300m_spi_info, 2);
/* register gpio LEDs and keys */
ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_ar300m_leds_gpio),
gl_ar300m_leds_gpio);
ath79_register_gpio_keys_polled(-1, GL_AR300M_KEYS_POLL_INTERVAL,
ARRAY_SIZE(gl_ar300m_gpio_keys),
gl_ar300m_gpio_keys);
ath79_register_mdio(0, 0x0);
/* WAN */
ath79_init_mac(ath79_eth0_data.mac_addr, art + GL_AR300M_MAC0_OFFSET, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, art + GL_AR300M_MAC1_OFFSET, 0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
ath79_init_mac(tmpmac, art + GL_AR300M_WMAC_CALDATA_OFFSET + 2, 0);
ath79_register_wmac(art + GL_AR300M_WMAC_CALDATA_OFFSET, tmpmac);
/* enable usb */
ath79_register_usb();
/* enable pci */
ath79_register_pci();
}
static void __init wzr_450hp2_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac_wan = art;
u8 *mac_lan = mac_wan + ETH_ALEN;
ath79_register_m25p80(&wzr_450hp2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wzr_450hp2_leds_gpio),
wzr_450hp2_leds_gpio);
ath79_register_gpio_keys_polled(-1, WZR_450HP2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wzr_450hp2_gpio_keys),
wzr_450hp2_gpio_keys);
ath79_register_wmac(art + WZR_450HP2_WMAC_CALDATA_OFFSET, mac_lan);
mdiobus_register_board_info(wzr_450hp2_mdio0_info,
ARRAY_SIZE(wzr_450hp2_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_init_mac(ath79_eth0_data.mac_addr, mac_wan, 0);
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_init_mac(ath79_eth1_data.mac_addr, mac_lan, 0);
ath79_register_eth(1);
ath79_register_usb();
}
static void __init tl_wr841n_v8_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio),
tl_wr841n_v8_leds_gpio);
ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr841n_v8_gpio_keys),
tl_wr841n_v8_gpio_keys);
/* enable power for the USB port */
gpio_request(TL_WR841NV8_GPIO_USB_POWER, "USB power");
gpio_direction_input(TL_WR841NV8_GPIO_USB_POWER);
ath79_register_usb();
/* END for the USB port */
ath79_register_m25p80(&tl_wr841n_v8_flash_data);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
static void __init wa161dd_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
ath79_register_m25p80(&huawei_wa161dd_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(huawei_wa161dd_leds_gpio),
huawei_wa161dd_leds_gpio);
ath79_register_gpio_keys_polled(-1, HUAWEI_WA161DD_KEYS_POLL_INTERVAL,
ARRAY_SIZE(huawei_wa161dd_gpio_keys),
huawei_wa161dd_gpio_keys);
tplink_register_builtin_wmac1(HUAWEI_WA161DD_WMAC_CALDATA_OFFSET, mac, -1);
tplink_register_ap91_wmac2(HUAWEI_WA161DD_PCIE_CALDATA_OFFSET, mac, 2);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
mdiobus_register_board_info(mi124_mdio0_info,
ARRAY_SIZE(mi124_mdio0_info));
/* GMAC0 is connected to an AR8035 Gigabit PHY */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x0e000000;
ath79_eth0_pll_data.pll_100 = 0x0101;
ath79_eth0_pll_data.pll_10 = 0x1313;
ath79_register_eth(0);
ath79_register_usb();
gpio_request_one(HUAWEI_WA161DD_GPIO_LED_GREEN_LAN_POLARITY,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"LAN LED Polarity");
}
static void __init sc1750_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(sc1750_leds_gpio),
sc1750_leds_gpio);
ath79_register_gpio_keys_polled(-1, SC1750_KEYS_POLL_INTERVAL,
ARRAY_SIZE(sc1750_gpio_keys),
sc1750_gpio_keys);
ath79_register_usb();
ath79_register_nfc();
ath79_register_wmac(art + SC1750_WMAC_CALDATA_OFFSET, NULL);
ath79_register_mdio(0, 0);
mdiobus_register_board_info(sc1750_mdio0_info,
ARRAY_SIZE(sc1750_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art + SC1750_MAC0_OFFSET, 0);
ath79_eth0_pll_data.pll_1000 = 0xa6000101;
ath79_eth0_pll_data.pll_100 = 0xa4000101;
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = 0xF;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
ath79_register_pci();
}
static void __init wpe72_setup(void)
{
ath79_register_m25p80(&wpe72_flash_data);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_usb();
ath79_register_pci();
ath79_register_leds_gpio(-1, ARRAY_SIZE(wpe72_leds_gpio),
wpe72_leds_gpio);
ath79_register_gpio_keys_polled(-1, WPE72_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wpe72_gpio_keys),
wpe72_gpio_keys);
}
static void __init weio_setup(void)
{
weio_common_setup();
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
platform_device_register(&weio_i2c_gpio);
ath79_register_leds_gpio(-1, ARRAY_SIZE(weio_leds_gpio),
weio_leds_gpio);
ath79_register_gpio_keys_polled(-1, WEIO_KEYS_POLL_INTERVAL,
ARRAY_SIZE(weio_gpio_keys),
weio_gpio_keys);
ath79_register_usb();
}
static void __init wndr4300_setup(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(wndr4300_leds_gpio); i++)
ath79_gpio_output_select(wndr4300_leds_gpio[i].gpio,
AR934X_GPIO_OUT_GPIO);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr4300_leds_gpio),
wndr4300_leds_gpio);
ath79_register_gpio_keys_polled(-1, WNDR4300_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wndr4300_gpio_keys),
wndr4300_gpio_keys);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(wndr4300_mdio0_info,
ARRAY_SIZE(wndr4300_mdio0_info));
ath79_register_mdio(0, 0x0);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
ath79_register_nfc();
ath79_register_usb();
ath79_register_wmac_simple();
/* enable power for the USB port */
ap9x_pci_setup_wmac_gpio(0, BIT(WNDR4300_GPIO_USB_5V),
BIT(WNDR4300_GPIO_USB_5V));
ap91_pci_init_simple();
}
static void __init ap132_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap132_leds_gpio),
ap132_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP132_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap132_gpio_keys),
ap132_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + AP132_WMAC_CALDATA_OFFSET, NULL);
/* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
ap132_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
ap132_ar8327_pad0_cfg.sgmii_delay_en = true;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ap132_mdio_setup();
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + AP132_MAC0_OFFSET, 0);
mdiobus_register_board_info(ap132_mdio1_info,
ARRAY_SIZE(ap132_mdio1_info));
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.phy_mask = BIT(0);
ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(1);
}
static void __init smart_300_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_leds_gpio(-1, ARRAY_SIZE(smart_300_leds_gpio),
smart_300_leds_gpio);
ath79_register_gpio_keys_polled(1, SMART_300_KEYS_POLL_INTERVAL,
ARRAY_SIZE(smart_300_gpio_keys),
smart_300_gpio_keys);
ath79_register_m25p80(&smart_300_flash_data);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
gpio_request(SMART_300_GPIO_LED_POWER, "power");
gpio_direction_output(SMART_300_GPIO_LED_POWER, GPIOF_OUT_INIT_LOW);
ath79_register_usb();
}
static void __init dr34x_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
ath79_register_m25p80(NULL);
ath79_gpio_direction_select(DR34X_GPIO_LED_STATUS, true);
gpio_set_value(DR34X_GPIO_LED_STATUS, 1);
ath79_gpio_output_select(DR34X_GPIO_LED_STATUS, 0);
ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dr34x_gpio_keys),
dr34x_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + DR34X_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(dr34x_mdio0_info,
ARRAY_SIZE(dr34x_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
/* GMAC0 is connected to an AR8035 Gbps PHY */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x02000000;
ath79_eth0_pll_data.pll_100 = 0x0101;
ath79_eth0_pll_data.pll_10 = 0x1313;
ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR34X_MAC0_OFFSET, 0);
ath79_register_eth(0);
}
static void __init dir_505_a1_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(DIR_505A1_ART_ADDRESS);
u8 lan_mac[ETH_ALEN];
u8 wan_mac[ETH_ALEN];
ath79_setup_ar933x_phy4_switch(false, false);
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
gpio_request_one(DIR_505A1_GPIO_WAN_LED_ENABLE,
GPIOF_OUT_INIT_LOW, "WAN LED enable");
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_505_a1_leds_gpio),
dir_505_a1_leds_gpio);
ath79_register_gpio_keys_polled(1, DIR_505A1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir_505_a1_gpio_keys),
dir_505_a1_gpio_keys);
ath79_register_m25p80(NULL);
ath79_register_usb();
dir_505_a1_read_ascii_mac(lan_mac, DIR_505A1_LAN_MAC_ADDRESS);
dir_505_a1_read_ascii_mac(wan_mac, DIR_505A1_WAN_MAC_ADDRESS);
ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(1);
ath79_register_eth(0);
ath79_register_wmac(art + DIR_505A1_CALDATA_OFFSET, lan_mac);
}
static void __init ds_setup(void)
{
u32 t=0;
ds_common_setup();
ath79_register_leds_gpio(-1, ARRAY_SIZE(ds_leds_gpio), ds_leds_gpio);
ath79_register_gpio_keys_polled(-1, DS_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ds_gpio_keys), ds_gpio_keys);
ath79_register_usb();
// use the swtich_led directly form sysfs
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN);
/*
* Disable the Function for some pins to have GPIO functionality active
* GPIO6-7-8 and GPIO11
*/
ath79_gpio_function_setup(GPIO_FUNC_SET, GPIO_FUNC_CLEAR);
ath79_gpio_function2_setup(GPIO_FUNC2_SET, GPIO_FUNC2_CLEAR);
pr_info("mach-linino: setting GPIO\n");
/* Enable GPIO26 instead of MDC function */
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
/* enable OE of level shifters */
ds_setup_level_shifter_oe();
/* enable uart */
ds_setup_uart_enable();
/* Register Software SPI controller */
ds_register_spi();
}
static void __init wnr_common_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_m25p80(NULL);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V4_MAC0_OFFSET, 0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V4_MAC1_OFFSET, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
/* WLAN */
ath79_register_wmac(ee, art+WNR2000V4_MAC0_OFFSET);
/* USB */
ath79_register_usb();
}
static void __init ap136_common_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
ap136_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap136_gpio_keys),
ap136_gpio_keys);
ath79_register_usb();
ath79_register_nfc();
ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
mdiobus_register_board_info(ap136_mdio0_info,
ARRAY_SIZE(ap136_mdio0_info));
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected tot eh SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
}
static void __init wrt160nl_setup(void)
{
const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR);
u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
u8 mac[6];
if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE,
"lan_hwaddr=", mac) == 0) {
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
}
ath79_register_mdio(0, 0x0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
ath79_eth0_data.phy_mask = 0x01;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
ath79_eth1_data.phy_mask = 0x10;
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_m25p80(&wrt160nl_flash_data);
ath79_register_usb();
if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE,
"wl0_hwaddr=", mac) == 0)
ath79_register_wmac(eeprom, mac);
else
ath79_register_wmac(eeprom, NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio),
wrt160nl_leds_gpio);
ath79_register_gpio_keys_polled(-1, WRT160NL_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wrt160nl_gpio_keys),
wrt160nl_gpio_keys);
}
