void audiohw_postinit(void)
{
sleep(5*HZ/4);
/* 7. Enable other mixers as required */
/* 8. Enable other outputs as required */
/* 9. Set remaining registers */
wmc_write(WMC_AUDIO_INTERFACE, WMC_WL_16 | WMC_FMT_I2S);
wmc_write(WMC_DAC_CONTROL, WMC_DACOSR_128);
/* No ADC, no HP filter, no popping */
wmc_clear(WMC_ADC_CONTROL, WMC_HPFEN);
wmc_clear(WMC_LEFT_ADC_BOOST_CTRL, WMC_PGABOOSTL);
wmc_clear(WMC_RIGHT_ADC_BOOST_CTRL, WMC_PGABOOSTR);
/* Specific to HW clocking */
wmc_write_masked(WMC_CLOCK_GEN_CTRL, WMC_BCLKDIV_4 | WMC_MS,
WMC_BCLKDIV | WMC_MS | WMC_CLKSEL);
audiohw_set_frequency(HW_FREQ_DEFAULT);
audiohw_enable_headphone_jack(true);
}
void pcm_play_dma_init(void)
{
IO_CLK_O1DIV = 3;
/* Set GIO25 to CLKOUT1A */
IO_GIO_FSEL2 |= 3;
sleep(5);
audiohw_init();
audiohw_set_frequency(HW_FREQ_DEFAULT);
/* init DSP */
// dsp_init();
}
/* Reset and power up the WM8751 */
void audiohw_preinit(void)
{
#ifdef MROBE_100
/* controls headphone ouput */
GPIOL_ENABLE |= 0x10;
GPIOL_OUTPUT_EN |= 0x10;
GPIOL_OUTPUT_VAL |= 0x10; /* disable */
#endif
#ifdef MPIO_HD200
/* control headphone output
* disabled on startup
*/
and_l(~(1<<25),&GPIO1_OUT);
or_l((1<<25), &GPIO1_ENABLE);
or_l((1<<25), &GPIO1_FUNCTION);
#endif
/*
* 1. Switch on power supplies.
* By default the WM8751 is in Standby Mode, the DAC is
* digitally muted and the Audio Interface, Line outputs
* and Headphone outputs are all OFF (DACMU = 1 Power
* Management registers 1 and 2 are all zeros).
*/
wmcodec_write(RESET, RESET_RESET); /*Reset*/
/* 2. Enable Vmid and VREF. */
wmcodec_set_bits(PWRMGMT1, PWRMGMT1_VREF | PWRMGMT1_VMIDSEL_5K);
#ifdef CODEC_SLAVE
wmcodec_set_bits(AINTFCE,AINTFCE_WL_16 | AINTFCE_FORMAT_I2S);
#else
/* BCLKINV=0(Dont invert BCLK) MS=1(Enable Master) LRSWAP=0 LRP=0 */
/* IWL=00(16 bit) FORMAT=10(I2S format) */
wmcodec_set_bits(AINTFCE, AINTFCE_MS | AINTFCE_WL_16 |
AINTFCE_FORMAT_I2S);
#endif
/* Set default samplerate */
audiohw_set_frequency(HW_FREQ_DEFAULT);
}
/*
* Ralink Audio System Clock Enable
*
* I2S_WS : signal direction opposite to/same as I2S_CLK
*
* I2S_CLK : Integer division or fractional division
* REFCLK from Internal or External (external REFCLK not support for fractional division)
* Suppose external REFCLK always be the same as external MCLK
*
* MCLK : External OSC or internal generation
*
*/
int i2s_clock_enable(i2s_config_type* ptri2s_config)
{
unsigned long data;
unsigned long index;
unsigned long* pTable;
/* audio sampling rate decision */
switch(ptri2s_config->srate)
{
case 8000:
index = 0;
break;
case 11025:
index = 1;
break;
case 12000:
index = 2;
break;
case 16000:
index = 3;
break;
case 22050:
index = 4;
break;
case 24000:
index = 5;
break;
case 32000:
index = 6;
break;
case 44100:
index = 7;
break;
case 48000:
index = 8;
break;
case 88200:
index = 9;
break;
case 96000:
index = 10;
break;
default:
index = 7;
}
/* enable internal MCLK */
#if defined(CONFIG_I2S_IN_MCLK)
#if defined(CONFIG_RALINK_RT63365)
//FIXME
#else
data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
#endif
#if defined(CONFIG_I2S_MCLK_12MHZ)
MSG("Enable SoC MCLK 12Mhz\n");
#if defined(CONFIG_RALINK_RT3350)
data |= (0x1<<8);
#elif defined(CONFIG_RALINK_RT3883)
data &= ~(0x03<<13);
data |= (0x1<<13);
#elif defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
data &= ~(0x0F<<8);
data |= (0x3<<8);
#elif defined(CONFIG_RALINK_RT63365)
//FIXME
#else
#error "This SoC do not provide MCLK to audio codec\n");
#endif
#endif
#if defined(CONFIG_I2S_MCLK_12P288MHZ)
MSG("Enable SoC MCLK 12.288Mhz\n");
#if defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
data &= ~(0x01F<<18);
data |= 31<<18;
data &= ~(0x01F<<12);
data |= 1<<12;
data |= (0xF<<8);
#elif defined(CONFIG_RALINK_RT63365)
#else
#error "This SoC do not provide MCLK 12.288Mhz audio codec\n");
#endif
#endif
#if defined(CONFIG_RALINK_RT63365)
#else
i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
#endif
#else
MSG("Disable SoC MCLK, use external OSC\n");
#if defined(CONFIG_RALINK_RT63365)
#else
data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
#endif
#if defined(CONFIG_RALINK_RT3350)
data &= ~(0x1<<8);
#elif defined(CONFIG_RALINK_RT3883)
#elif defined(CONFIG_RALINK_RT3352)
data &= ~(0x0F<<8);
#elif defined(CONFIG_RALINK_RT5350)
data |= (0x0F<<8);
#elif defined (CONFIG_RALINK_RT6855)
data &= ~(0x0F<<8);
#endif
#if defined(CONFIG_RALINK_RT63365)
#else
i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
#endif
#endif
/* set share pins to i2s/gpio mode and i2c mode */
#if defined(CONFIG_RALINK_RT63365)
data = i2s_inw(RALINK_SYSCTL_BASE+0x860);
data |= 0x00008080;
i2s_outw(RALINK_SYSCTL_BASE+0x860, data);
#else
data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
data &= 0xFFFFFFE2;
data |= 0x00000018;
i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
#endif
if(ptri2s_config->slave_en==0)
{
/* Setup I2S_WS and I2S_CLK */
#if defined(CONFIG_I2S_IN_CLK)
/* REFCLK is 15.625Mhz or 40Mhz(fractional division) */
#if defined(CONFIG_I2S_FRAC_DIV)
MSG("Internal REFCLK with fractional division\n");
pTable = i2sMaster_inclk_int;
data = (unsigned long)(pTable[index]);
i2s_outw(I2S_DIVINT_CFG, data);
pTable = i2sMaster_inclk_comp;
data = (unsigned long)(pTable[index]);
data |= REGBIT(1, I2S_CLKDIV_EN);
i2s_outw(I2S_DIVCOMP_CFG, data);
#else
MSG("Internal REFCLK 15.625Mhz \n");
pTable = i2sMaster_inclk_15p625Mhz;
data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
data &= 0xFFFF00FF;
data |= (unsigned long)(pTable[index]);
data |= 0x00008000;
i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
#endif
#else
#if defined(CONFIG_I2S_MCLK_12MHZ)
/* REFCLK = MCLK = 12Mhz */
MSG("External REFCLK 12Mhz \n");
pTable = i2sMaster_exclk_12Mhz;
data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
data &= 0xFFFF00FF;
data |= (unsigned long)(pTable[index]);
data |= 0x0000C000;
i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
#else
/* REFCLK = MCLK = 12.288Mhz */
pTable = i2sMaster_exclk_12p288Mhz;
MSG("External REFCLK 12.288Mhz \n");
data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
data &= 0xFFFF00FF;
data |= (unsigned long)(pTable[index]);
data |= 0x0000C000;
i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
#endif
#endif /* Not CONFIG_I2S_IN_CLK */
#if defined(CONFIG_I2S_WS_EDGE)
data = i2s_inw(I2S_I2SCFG);
data |= REGBIT(0x1, I2S_WS_INV);
i2s_outw(I2S_I2SCFG, data);
#endif
#if defined(CONFIG_RALINK_RT3052)
data = i2s_inw(I2S_I2SCFG);
data &= ~REGBIT(0x1, I2S_SLAVE_EN);
data &= ~REGBIT(0x1, I2S_CLK_OUT_DIS);
i2s_outw(I2S_I2SCFG, data);
#elif defined(CONFIG_RALINK_RT3883)||defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) ||\
defined(CONFIG_RALINK_RT63365)
data = i2s_inw(I2S_I2SCFG);
data &= ~REGBIT(0x1, I2S_SLAVE_MODE);
i2s_outw(I2S_I2SCFG, data);
#else
#error "a strange clock mode"
#endif
i2s_codec_enable(ptri2s_config);
#if defined(CONFIG_I2S_MCLK_12MHZ)
pTable = i2sSlave_exclk_12Mhz;
data = pTable[index];
audiohw_set_frequency(data|0x01);
#else
pTable = i2sSlave_exclk_12p288Mhz;
data = pTable[index];
audiohw_set_frequency(data);
#endif
}
else
{
#if defined(CONFIG_RALINK_RT3052)
data = i2s_inw(I2S_I2SCFG);
data |= REGBIT(0x1, I2S_SLAVE_EN);
data |= REGBIT(0x1, I2S_CLK_OUT_DIS);
i2s_outw(I2S_I2SCFG, data);
#elif defined(CONFIG_RALINK_RT3883)||defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) ||\
defined(CONFIG_RALINK_RT63365)
data = i2s_inw(I2S_I2SCFG);
data |= REGBIT(0x1, I2S_SLAVE_MODE);
i2s_outw(I2S_I2SCFG, data);
#else
#error "a strange clock mode "
#endif
i2s_codec_enable(ptri2s_config);
#if defined(CONFIG_I2S_MCLK_12MHZ)
pTable = i2sSlave_exclk_12Mhz;
data = pTable[index];
audiohw_set_frequency(data|0x1); /* for MCLK=12Mhz only. */
#else
pTable = i2sSlave_exclk_12p288Mhz;
data = pTable[index];
audiohw_set_frequency(data);
#endif
}
return 0;
}
void pcm_dma_apply_settings(void)
{
audiohw_set_frequency(pcm_fsel);
}
static int i2s_dev_open(i2s_config_type* ptri2s_config)
{
int i, result, db, srate;
unsigned int data = 0;
MSG("i2s_dev_open \n");
/* set i2s clk */
data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
data &= 0xFFFF00FF;
#ifdef I2S_MS_MODE
#ifdef I2S_IN_CLKSRC
data |= 0x00008000;
/* for internal clock = 15.625 Mhz */
switch(ptri2s_config->srate)
{
case 8000:
srate = 60<<8;
break;
case 11250:
srate = 43<<8;
break;
case 16000:
srate = 30<<8;
break;
case 22050:
srate = 21<<8;
break;
case 24000:
srate = 19<<8;
break;
case 32000:
srate = 14<<8;
break;
case 44100:
srate = 10<<8;
break;
case 48000:
srate = 9<<8;
break;
case 88200:
srate = 7<<8;
break;
case 96000:
srate = 4<<8;
break;
default:
srate = 10<<8;
}
#ifdef FPGA_BOARD_RT3052
/* for internal clock = 12.5Mhz */
switch(ptri2s_config->srate)
{
case 8000:
srate = 48<<8;
break;
case 11250:
srate = 34<<8;
break;
case 16000:
srate = 23<<8;
break;
case 22050:
srate = 17<<8;
break;
case 24000:
srate = 15<<8;
break;
case 32000:
srate = 11<<8;
break;
case 44100:
srate = 8<<8;
break;
case 48000:
srate = 7<<8;
break;
case 88200:
srate = 5<<8;
break;
case 96000:
srate = 3<<8;
break;
default:
srate = 8<<8;
}
#endif
#else
data |= 0x0000C000;
/* for external clock = 12.288Mhz */
switch(ptri2s_config->srate)
{
case 8000:
srate = 48<<8;
break;
case 11250:
srate = 34<<8;
break;
case 16000:
srate = 23<<8;
break;
case 22050:
srate = 17<<8;
break;
case 24000:
srate = 15<<8;
break;
case 32000:
srate = 11<<8;
break;
case 44100:
srate = 8<<8;
break;
case 48000:
srate = 7<<8;
break;
case 88200:
srate = 5<<8;
break;
case 96000:
srate = 3<<8;
break;
default:
srate = 8<<8;
}
#endif
data |= srate;
#else
/* for external clock = 12.288Mhz, I2S slave mode */
switch(ptri2s_config->srate)
{
case 8000:
srate = 0x04;
break;
case 11250:
srate = 0x10;
break;
case 16000:
srate = 0x14;
break;
case 22050:
srate = 0x38;
break;
case 24000:
srate = 0x38;
break;
case 32000:
srate = 0x18;
break;
case 44100:
srate = 0x20;
break;
case 48000:
srate = 0x00;
break;
case 88200:
srate = 0x00;
break;
case 96000:
srate = 0x1C;
break;
default:
srate = 0x20;
}
#endif
i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
MSG("RALINK_SYSCTL_BASE+0x30=0x%08X\n",data);
/* set share pins to i2c */
data = i2s_inw(RALINK_REG_GPIOMODE);
data &= 0xFFFFFFE0;
data |= 0x00000008;
i2s_outw(RALINK_REG_GPIOMODE, data);
MSG("RALINK_REG_GPIOMODE=0x%08X\n",data);
/* DAC initialization */
audiohw_preinit();
audiohw_postinit();
#ifdef I2S_MS_MODE
#else
audiohw_set_frequency(srate);
#endif
//saudiohw_enable_output();
//db = tenthdb2master(ptri2s_config->vol);
//audiohw_set_lineout_vol(db, db);
/* set I2S_I2SCFG */
data = i2s_inw(I2S_I2SCFG);
data &= 0xFFFFFF80;
data |= REGBIT(ptri2s_config->ff_thres, I2S_FF_THRES);
data |= REGBIT(ptri2s_config->ch_swap, I2S_CH_SWAP);
#ifdef I2S_MS_MODE
data &= ~REGBIT(0x1, I2S_SLAVE_EN);
data &= ~REGBIT(0x1, I2S_CLK_OUT_DIS);
#else
data |= REGBIT(0x1, I2S_SLAVE_EN);
data |= REGBIT(0x1, I2S_CLK_OUT_DIS);
#endif
i2s_outw(I2S_I2SCFG, data);
MSG("I2S_I2SCFG=%X\n",data);
i2s_dev_enable(ptri2s_config);
return I2S_OK;
}
