/**
* Verify that a BAM device is enabled and gathers the hardware
* configuration.
*
*/
int bam_check(void *base, u32 *version, u32 *num_pipes)
{
u32 ver = 0;
if (!bam_read_reg_field(base, CTRL, BAM_EN)) {
SPS_ERR("sps:%s:bam 0x%x(va) is not enabled.\n",
__func__, (u32) base);
return -ENODEV;
}
ver = bam_read_reg(base, REVISION) & BAM_REVISION;
/*
* Discover the hardware version number and the number of pipes
* supported by this BAM
*/
*num_pipes = bam_read_reg(base, NUM_PIPES);
*version = ver;
/* Check BAM version */
if ((ver < BAM_MIN_VERSION) || (ver > BAM_MAX_VERSION)) {
SPS_ERR("sps:%s:bam 0x%x(va) Invalid BAM version 0x%x.\n",
__func__, (u32) base, ver);
return -ENODEV;
}
return 0;
}
/**
* Get BAM IRQ source and clear global IRQ status
*/
u32 bam_check_irq_source(void *base, u32 ee, u32 mask,
enum sps_callback_case *cb_case)
{
u32 source = bam_read_reg(base, IRQ_SRCS_EE(ee));
u32 clr = source & (1UL << 31);
if (clr) {
u32 status = 0;
status = bam_read_reg(base, IRQ_STTS);
if (status & IRQ_STTS_BAM_ERROR_IRQ) {
SPS_ERR("sps:bam 0x%x(va);bam irq status="
"0x%x.\nsps: BAM_ERROR_IRQ\n",
(u32) base, status);
bam_output_register_content(base);
*cb_case = SPS_CALLBACK_BAM_ERROR_IRQ;
} else if (status & IRQ_STTS_BAM_HRESP_ERR_IRQ) {
SPS_ERR("sps:bam 0x%x(va);bam irq status="
"0x%x.\nsps: BAM_HRESP_ERR_IRQ\n",
(u32) base, status);
bam_output_register_content(base);
*cb_case = SPS_CALLBACK_BAM_HRESP_ERR_IRQ;
} else
SPS_INFO("sps:bam 0x%x(va);bam irq status="
"0x%x.", (u32) base, status);
bam_write_reg(base, IRQ_CLR, status);
}
source &= (mask|(1UL << 31));
return source;
}
/* output BAM_TEST_BUS_REG with specified TEST_BUS_SEL */
void print_bam_test_bus_reg(void *base, u32 tb_sel)
{
u32 i;
u32 test_bus_selection[] = {0x1, 0x2, 0x3, 0x4, 0xD, 0x10,
0x41, 0x42, 0x43, 0x44, 0x45, 0x46};
u32 size = sizeof(test_bus_selection) / sizeof(u32);
if ((base == NULL) || (tb_sel == 0))
return;
SPS_INFO("\nsps:Specified TEST_BUS_SEL value: 0x%x\n", tb_sel);
bam_write_reg_field(base, TEST_BUS_SEL, BAM_TESTBUS_SEL, tb_sel);
SPS_INFO("sps:BAM_TEST_BUS_REG: 0x%x when TEST_BUS_SEL: 0x%x\n\n",
bam_read_reg(base, TEST_BUS_REG),
bam_read_reg_field(base, TEST_BUS_SEL, BAM_TESTBUS_SEL));
/* output other selections */
for (i = 0; i < size; i++) {
bam_write_reg_field(base, TEST_BUS_SEL, BAM_TESTBUS_SEL,
test_bus_selection[i]);
SPS_INFO("sps:bam 0x%x(va);TEST_BUS_REG:0x%x;TEST_BUS_SEL:0x%x",
(u32) base, bam_read_reg(base, TEST_BUS_REG),
bam_read_reg_field(base, TEST_BUS_SEL,
BAM_TESTBUS_SEL));
}
}
int bam_check(void *base, u32 *version, u32 *num_pipes)
{
u32 ver = 0;
SPS_DBG2("sps:%s:bam=0x%x(va).", __func__, (u32) base);
if (!bam_read_reg_field(base, CTRL, BAM_EN)) {
SPS_ERR("sps:%s:bam 0x%x(va) is not enabled.\n",
__func__, (u32) base);
return -ENODEV;
}
ver = bam_read_reg(base, REVISION) & BAM_REVISION;
*num_pipes = bam_read_reg(base, NUM_PIPES);
*version = ver;
if ((ver < BAM_MIN_VERSION) || (ver > BAM_MAX_VERSION)) {
SPS_ERR("sps:%s:bam 0x%x(va) Invalid BAM version 0x%x.\n",
__func__, (u32) base, ver);
return -ENODEV;
}
return 0;
}
/**
* Output BAM register content
* including the TEST_BUS register content under
* different TEST_BUS_SEL values.
*/
static void bam_output_register_content(void *base)
{
u32 num_pipes;
u32 test_bus_selection[] = {0x1, 0x2, 0x3, 0x4, 0xD, 0x10,
0x41, 0x42, 0x43, 0x44, 0x45, 0x46};
u32 i;
u32 size = sizeof(test_bus_selection) / sizeof(u32);
for (i = 0; i < size; i++) {
bam_write_reg_field(base, TEST_BUS_SEL, BAM_TESTBUS_SEL,
test_bus_selection[i]);
SPS_INFO("sps:bam 0x%x(va);BAM_TEST_BUS_REG is"
"0x%x when BAM_TEST_BUS_SEL is 0x%x.",
(u32) base, bam_read_reg(base, TEST_BUS_REG),
bam_read_reg_field(base, TEST_BUS_SEL,
BAM_TESTBUS_SEL));
}
print_bam_reg(base);
num_pipes = bam_read_reg_field(base, NUM_PIPES,
BAM_NUM_PIPES);
SPS_INFO("sps:bam 0x%x(va) has %d pipes.",
(u32) base, num_pipes);
for (i = 0; i < num_pipes; i++)
print_bam_pipe_reg(base, i);
}
/**
* Get and Clear BAM pipe IRQ status
*
*/
u32 bam_pipe_get_and_clear_irq_status(void *base, u32 pipe)
{
u32 status = 0;
status = bam_read_reg(base, P_IRQ_STTS(pipe));
bam_write_reg(base, P_IRQ_CLR(pipe), status);
return status;
}
/**
* Get and Clear BAM global IRQ status
*
* note: clear status only for pipes controlled by this
* processor
*/
u32 bam_get_and_clear_irq_status(void *base, u32 ee, u32 mask)
{
u32 status = bam_read_reg(base, IRQ_SRCS);
u32 clr = status &= mask;
bam_write_reg(base, IRQ_CLR, clr);
return status;
}
/**
* Initialize a BAM device
*
*/
int bam_init(void *base, u32 ee,
u16 summing_threshold,
u32 irq_mask, u32 *version, u32 *num_pipes)
{
/* disable bit#11 because of HW bug */
u32 cfg_bits = 0xffffffff & ~(1 << 11);
u32 ver = 0;
ver = bam_read_reg(base, REVISION);
if ((ver < BAM_MIN_VERSION) || (ver > BAM_MAX_VERSION)) {
pr_err("bam:Invalid BAM version 0x%x.\n", ver);
return -ENODEV;
}
if (summing_threshold == 0) {
summing_threshold = 4;
pr_err("bam:summing_threshold is zero , use default 4.\n");
}
bam_write_reg_field(base, CTRL, BAM_SW_RST, 1);
/* No delay needed */
bam_write_reg_field(base, CTRL, BAM_SW_RST, 0);
bam_write_reg_field(base, CTRL, BAM_EN, 1);
bam_write_reg(base, DESC_CNT_TRSHLD, summing_threshold);
bam_write_reg(base, CNFG_BITS, cfg_bits);
/*
* Enable Global BAM Interrupt - for error reasons ,
* filter with mask.
* Note: Pipes interrupts are disabled until BAM_P_IRQ_enn is set
*/
bam_write_reg_field(base, IRQ_SRCS_MSK, BAM_IRQ, 1);
bam_write_reg(base, IRQ_EN, irq_mask);
*num_pipes = bam_read_reg(base, NUM_PIPES);
*version = ver;
return 0;
}
/**
* Get BAM IRQ source and clear global IRQ status
*/
u32 bam_check_irq_source(void *base, u32 ee, u32 mask)
{
u32 source = bam_read_reg(base, IRQ_SRCS_EE(ee));
u32 clr = source & (1UL << 31);
if (clr) {
u32 status = 0;
status = bam_read_reg(base, IRQ_STTS);
bam_write_reg(base, IRQ_CLR, status);
if (printk_ratelimit()) {
if (status & IRQ_STTS_BAM_ERROR_IRQ)
SPS_ERR("sps:bam 0x%x(va);bam irq status="
"0x%x.\nsps: BAM_ERROR_IRQ\n",
(u32) base, status);
else
SPS_INFO("sps:bam 0x%x(va);bam irq status="
"0x%x.", (u32) base, status);
}
}
source &= mask;
return source;
}
/* output the content of selected BAM-level registers */
void print_bam_selected_reg(void *virt_addr)
{
void *base = virt_addr;
if (base == NULL)
return;
SPS_INFO("\nsps:----- Content of BAM-level registers <begin> -----\n");
SPS_INFO("BAM_CTRL: 0x%x\n"
"BAM_REVISION: 0x%x\n"
"BAM_NUM_EES: %d\n"
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
"BAM_CMD_DESC_EN: 0x%x\n"
#endif
"BAM_NUM_PIPES: %d\n"
"BAM_DESC_CNT_TRSHLD: 0x%x (%d)\n"
"BAM_IRQ_SRCS: 0x%x\n"
"BAM_IRQ_SRCS_MSK: 0x%x\n"
"BAM_EE: %d\n"
"BAM_CNFG_BITS: 0x%x\n",
bam_read_reg(base, CTRL),
bam_read_reg_field(base, REVISION, BAM_REVISION),
bam_read_reg_field(base, REVISION, BAM_NUM_EES),
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
bam_read_reg_field(base, REVISION, BAM_CMD_DESC_EN),
#endif
bam_read_reg_field(base, NUM_PIPES, BAM_NUM_PIPES),
bam_read_reg_field(base, DESC_CNT_TRSHLD, BAM_DESC_CNT_TRSHLD),
bam_read_reg_field(base, DESC_CNT_TRSHLD, BAM_DESC_CNT_TRSHLD),
bam_read_reg(base, IRQ_SRCS),
bam_read_reg(base, IRQ_SRCS_MSK),
bam_read_reg_field(base, TRUST_REG, BAM_EE),
bam_read_reg(base, CNFG_BITS));
SPS_INFO("\nsps:----- Content of BAM-level registers <end> -----\n");
}
/**
* Verify that a BAM device is enabled and gathers the hardware
* configuration.
*
*/
int bam_check(void *base, u32 *version, u32 *num_pipes)
{
u32 ver = 0;
if (!bam_read_reg_field(base, CTRL, BAM_EN))
return -ENODEV;
ver = bam_read_reg(base, REVISION);
/*
* Discover the hardware version number and the number of pipes
* supported by this BAM
*/
*num_pipes = bam_read_reg(base, NUM_PIPES);
*version = ver;
/* Check BAM version */
if ((ver < BAM_MIN_VERSION) || (ver > BAM_MAX_VERSION)) {
pr_err("bam:Invalid BAM version 0x%x.\n", ver);
return -ENODEV;
}
return 0;
}
/* output descriptor FIFO of a pipe */
void print_bam_pipe_desc_fifo(void *virt_addr, u32 pipe_index)
{
void *base = virt_addr;
u32 pipe = pipe_index;
u32 desc_fifo_addr;
u32 desc_fifo_size;
u32 *desc_fifo;
int i;
if (base == NULL)
return;
desc_fifo_addr = bam_read_reg(base, P_DESC_FIFO_ADDR(pipe));
desc_fifo_size = bam_read_reg_field(base, P_FIFO_SIZES(pipe),
P_DESC_FIFO_SIZE);
if (desc_fifo_addr == 0) {
SPS_ERR("sps:%s:desc FIFO address of Pipe %d is NULL.\n",
__func__, pipe);
return;
} else if (desc_fifo_size == 0) {
SPS_ERR("sps:%s:desc FIFO size of Pipe %d is 0.\n",
__func__, pipe);
return;
}
SPS_INFO("\nsps:----- descriptor FIFO of Pipe %d -----\n", pipe);
SPS_INFO("BAM_P_DESC_FIFO_ADDR: 0x%x\n"
"BAM_P_DESC_FIFO_SIZE: 0x%x (%d)\n\n",
desc_fifo_addr, desc_fifo_size, desc_fifo_size);
desc_fifo = (u32 *) phys_to_virt(desc_fifo_addr);
SPS_INFO("-------------------- begin of FIFO --------------------\n");
for (i = 0; i < desc_fifo_size; i += 0x10)
SPS_INFO("addr 0x%x: 0x%x, 0x%x, 0x%x, 0x%x.\n",
desc_fifo_addr + i,
desc_fifo[i / 4], desc_fifo[(i / 4) + 1],
desc_fifo[(i / 4) + 2], desc_fifo[(i / 4) + 3]);
SPS_INFO("-------------------- end of FIFO --------------------\n");
}
/* output the content of selected BAM pipe registers */
void print_bam_pipe_selected_reg(void *virt_addr, u32 pipe_index)
{
void *base = virt_addr;
u32 pipe = pipe_index;
if (base == NULL)
return;
SPS_INFO("\nsps:----- Registers of Pipe %d -----\n", pipe);
SPS_INFO("BAM_P_CTRL: 0x%x\n"
"BAM_P_SYS_MODE: %d\n"
"BAM_P_DIRECTION: %d\n"
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
"BAM_P_LOCK_GROUP: 0x%x (%d)\n"
#endif
"BAM_P_EE: %d\n"
"BAM_P_IRQ_STTS: 0x%x\n"
"BAM_P_IRQ_STTS_P_TRNSFR_END_IRQ: 0x%x\n"
"BAM_P_IRQ_STTS_P_PRCSD_DESC_IRQ: 0x%x\n"
"BAM_P_IRQ_EN: %d\n"
"BAM_P_PRDCR_SDBNDn_BAM_P_BYTES_FREE: 0x%x (%d)\n"
"BAM_P_CNSMR_SDBNDn_BAM_P_BYTES_AVAIL: 0x%x (%d)\n"
"BAM_P_SW_DESC_OFST: 0x%x\n"
"BAM_P_DESC_FIFO_PEER_OFST: 0x%x\n"
"BAM_P_EVNT_DEST_ADDR: 0x%x\n"
"BAM_P_DESC_FIFO_ADDR: 0x%x\n"
"BAM_P_DESC_FIFO_SIZE: 0x%x (%d)\n"
"BAM_P_DATA_FIFO_ADDR: 0x%x\n"
"BAM_P_DATA_FIFO_SIZE: 0x%x (%d)\n"
"BAM_P_EVNT_GEN_TRSHLD: 0x%x (%d)\n",
bam_read_reg(base, P_CTRL(pipe)),
bam_read_reg_field(base, P_CTRL(pipe), P_SYS_MODE),
bam_read_reg_field(base, P_CTRL(pipe), P_DIRECTION),
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
bam_read_reg_field(base, P_CTRL(pipe), P_LOCK_GROUP),
bam_read_reg_field(base, P_CTRL(pipe), P_LOCK_GROUP),
#endif
bam_read_reg_field(base, P_TRUST_REG(pipe), BAM_P_EE),
bam_read_reg(base, P_IRQ_STTS(pipe)),
bam_read_reg_field(base, P_IRQ_STTS(pipe),
P_IRQ_STTS_P_TRNSFR_END_IRQ),
bam_read_reg_field(base, P_IRQ_STTS(pipe),
P_IRQ_STTS_P_PRCSD_DESC_IRQ),
bam_read_reg(base, P_IRQ_EN(pipe)),
bam_read_reg_field(base, P_PRDCR_SDBND(pipe),
P_PRDCR_SDBNDn_BAM_P_BYTES_FREE),
bam_read_reg_field(base, P_PRDCR_SDBND(pipe),
P_PRDCR_SDBNDn_BAM_P_BYTES_FREE),
bam_read_reg_field(base, P_CNSMR_SDBND(pipe),
P_CNSMR_SDBNDn_BAM_P_BYTES_AVAIL),
bam_read_reg_field(base, P_CNSMR_SDBND(pipe),
P_CNSMR_SDBNDn_BAM_P_BYTES_AVAIL),
bam_read_reg_field(base, P_SW_OFSTS(pipe), SW_DESC_OFST),
bam_read_reg_field(base, P_EVNT_REG(pipe),
P_DESC_FIFO_PEER_OFST),
bam_read_reg(base, P_EVNT_DEST_ADDR(pipe)),
bam_read_reg(base, P_DESC_FIFO_ADDR(pipe)),
bam_read_reg_field(base, P_FIFO_SIZES(pipe), P_DESC_FIFO_SIZE),
bam_read_reg_field(base, P_FIFO_SIZES(pipe), P_DESC_FIFO_SIZE),
bam_read_reg(base, P_DATA_FIFO_ADDR(pipe)),
bam_read_reg_field(base, P_FIFO_SIZES(pipe), P_DATA_FIFO_SIZE),
bam_read_reg_field(base, P_FIFO_SIZES(pipe), P_DATA_FIFO_SIZE),
bam_read_reg_field(base, P_EVNT_GEN_TRSHLD(pipe),
P_EVNT_GEN_TRSHLD_P_TRSHLD),
bam_read_reg_field(base, P_EVNT_GEN_TRSHLD(pipe),
P_EVNT_GEN_TRSHLD_P_TRSHLD));
}
/**
* Get inactivity timer count for a BAM pipe
*
*/
u32 bam_pipe_timer_get_count(void *base, u32 pipe)
{
return bam_read_reg(base, P_TIMER(pipe));
}
