rtems_status_code rtems_bsp_enable_interrupt(
uint32_t bank,
uint32_t pin,
rtems_gpio_interrupt interrupt
) {
/* Enable IRQ generation for the specific pin */
mmio_set(bbb_reg(bank, AM335X_GPIO_IRQSTATUS_SET_0), BIT(pin));
switch ( interrupt ) {
case FALLING_EDGE:
/* Enables asynchronous falling edge detection. */
mmio_set(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin));
break;
case RISING_EDGE:
/* Enables asynchronous rising edge detection. */
mmio_set(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin));
break;
case BOTH_EDGES:
/* Enables asynchronous falling edge detection. */
mmio_set(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin));
/* Enables asynchronous rising edge detection. */
mmio_set(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin));
break;
case LOW_LEVEL:
/* Enables pin low level detection. */
mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin));
break;
case HIGH_LEVEL:
/* Enables pin high level detection. */
mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin));
break;
case BOTH_LEVELS:
/* Enables pin low level detection. */
mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin));
/* Enables pin high level detection. */
mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin));
break;
case NONE:
default:
return RTEMS_UNSATISFIED;
}
/* The detection starts after 5 clock cycles as per AM335X TRM
* This period is required to clean the synchronization edge/
* level detection pipeline
*/
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
return RTEMS_SUCCESSFUL;
}
static rtems_status_code bbb_select_pin_function(
uint32_t bank,
uint32_t pin,
uint32_t type
) {
if ( type == BBB_DIGITAL_IN ) {
mmio_set(bbb_reg(bank, AM335X_GPIO_OE), BIT(pin));
} else {
mmio_clear(bbb_reg(bank, AM335X_GPIO_OE), BIT(pin));
}
return RTEMS_SUCCESSFUL;
}
uint32_t rtems_gpio_bsp_interrupt_line(rtems_vector_number vector)
{
uint32_t event_status;
uint8_t bank_nr = 0;
/* Following loop will get the bank number from vector number */
while (bank_nr < GPIO_BANK_COUNT && vector != gpio_bank_vector[bank_nr])
{
bank_nr++;
}
/* Retrieve the interrupt event status. */
event_status = mmio_read(bbb_reg(bank_nr, AM335X_GPIO_IRQSTATUS_0));
/* Clear the interrupt line. */
mmio_write(
(bbb_reg(bank_nr, AM335X_GPIO_IRQSTATUS_0)), event_status);
return event_status;
}
uint32_t rtems_gpio_bsp_get_value(uint32_t bank, uint32_t pin)
{
return (mmio_read(bbb_reg(bank, AM335X_GPIO_DATAIN)) & BIT(pin));
}
rtems_status_code rtems_gpio_bsp_clear(uint32_t bank, uint32_t pin)
{
mmio_set(bbb_reg(bank, AM335X_GPIO_CLEARDATAOUT), BIT(pin));
return RTEMS_SUCCESSFUL;
}
uint32_t rtems_gpio_bsp_multi_read(uint32_t bank, uint32_t bitmask)
{
return (bbb_reg(bank, AM335X_GPIO_DATAIN) & bitmask);
}
rtems_status_code rtems_gpio_bsp_multi_clear(uint32_t bank, uint32_t bitmask)
{
mmio_set(bbb_reg(bank, AM335X_GPIO_CLEARDATAOUT), bitmask);
return RTEMS_SUCCESSFUL;
}
