void bcm_phy_r_rc_cal_reset(struct phy_device *phydev) { /* Reset R_CAL/RC_CAL Engine */ bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010); /* Disable Reset R_AL/RC_CAL Engine */ bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000); }
static int bcm_cygnus_afe_config(struct phy_device *phydev) { int rc; /* ensure smdspclk is enabled */ rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30); if (rc < 0) return rc; /* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */ rc = bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8); if (rc < 0) return rc; /* AFE_HPF_TRIM_OTHERS bit11=1, short cascode enable for all modes*/ rc = bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803); if (rc < 0) return rc; /* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */ rc = bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740); if (rc < 0) return rc; /* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */ rc = bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400); if (rc < 0) return rc; /* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */ rc = bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004); if (rc < 0) return rc; /* Adjust bias current trim to overcome digital offSet */ rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02); if (rc < 0) return rc; /* make rcal=100, since rdb default is 000 */ rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB1, 0x10); if (rc < 0) return rc; /* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */ rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB0, 0x10); if (rc < 0) return rc; /* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */ rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB0, 0x00); return 0; }