static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) { if (cs) bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL); else bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0); }
static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b) { if (b != LED_OFF) bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); else bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); }
static void db1200_mmcled_set(struct led_classdev *led, enum led_brightness brightness) { if (brightness != LED_OFF) bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); else bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); }
static void db1300_movinand_led_set(struct led_classdev *led, enum led_brightness brightness) { if (brightness != LED_OFF) bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); else bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); }
static void db1200_mmc_set_power(void *mmc_host, int state) { if (state) { bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); msleep(400); /* stabilization time */ } else bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); }
static void db1100_mmc1_set_power(void *mmc_host, int state) { if (state) { bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); msleep(400); /* */ } else bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); }
static void db1100_mmc1_set_power(void *mmc_host, int state) { int bit; if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) bit = BCSR_BOARD_SD1PWR; else bit = BCSR_BOARD_PB1100_SD1PWR; if (state) { bcsr_mod(BCSR_BOARD, 0, bit); msleep(400); /* stabilization time */ } else bcsr_mod(BCSR_BOARD, bit, 0); }
static int db1300fb_panel_shutdown(void) { /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); return 0; }
int board_au1200fb_panel_init(void) { /* Apply power */ bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL); return 0; }
static int db1300fb_panel_init(void) { bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, BCSR_BOARD_LCDBL); return 0; }
static int db1300fb_panel_init(void) { /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, BCSR_BOARD_LCDBL); return 0; }
static int db1300fb_panel_shutdown(void) { bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); return 0; }
int board_au1200fb_panel_shutdown(void) { /* Remove power */ bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL, 0); return 0; }
int board_au1200fb_panel_shutdown(void) { /* Remove power */ bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL, 0); /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */ return 0; }
int board_au1200fb_panel_init(void) { /* Apply power */ bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL); /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */ return 0; }
static void db1000_irda_set_phy_mode(int mode) { unsigned short mask = BCSR_RESETS_IRDA_MODE_MASK | BCSR_RESETS_FIR_SEL; switch (mode) { case AU1000_IRDA_PHY_MODE_OFF: bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_OFF); break; case AU1000_IRDA_PHY_MODE_SIR: bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL); break; case AU1000_IRDA_PHY_MODE_FIR: bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL | BCSR_RESETS_FIR_SEL); break; } }
static int __init db1300_device_init(void) { int swapped, cpldirq; /* setup CPLD IRQ muxer */ cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1); irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH); bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq); /* insert/eject IRQs: one always triggers so don't enable them * when doing request_irq() on them. DB1200 has this bug too. */ irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN); irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN); irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN); irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN); /* * setup board */ prom_get_ethernet_addr(&db1300_eth_config.mac[0]); i2c_register_board_info(0, db1300_i2c_devs, ARRAY_SIZE(db1300_i2c_devs)); /* Audio PSC clock is supplied by codecs (PSC1, 2) */ __raw_writel(PSC_SEL_CLK_SERCLK, (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); __raw_writel(PSC_SEL_CLK_SERCLK, (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); /* I2C uses internal 48MHz EXTCLK1 */ __raw_writel(PSC_SEL_CLK_INTCLK, (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); /* enable power to USB ports */ bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR); /* although it is socket #0, it uses the CPLD bits which previous boards * have used for socket #1. */ db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR, AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1, AU1000_PCMCIA_MEM_PHYS_ADDR, AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1, AU1000_PCMCIA_IO_PHYS_ADDR, AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1, DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1); swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; db1x_register_norflash(64 << 20, 2, swapped); return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev)); }
static int __init db1300_device_init(void) { int swapped, cpldirq; cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1); irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH); bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq); irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN); irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN); irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN); irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN); prom_get_ethernet_addr(&db1300_eth_config.mac[0]); i2c_register_board_info(0, db1300_i2c_devs, ARRAY_SIZE(db1300_i2c_devs)); __raw_writel(PSC_SEL_CLK_SERCLK, (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); __raw_writel(PSC_SEL_CLK_SERCLK, (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); __raw_writel(PSC_SEL_CLK_INTCLK, (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR); db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR, AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1, AU1000_PCMCIA_MEM_PHYS_ADDR, AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1, AU1000_PCMCIA_IO_PHYS_ADDR, AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1, DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1); swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; db1x_register_norflash(64 << 20, 2, swapped); return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev)); }
void __init board_setup(void) { printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); bcsr_init(PB1200_BCSR_PHYS_ADDR, PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); #if 0 { u32 pin_func; /* * Enable PSC1 SYNC for AC97. Normaly done in audio driver, * but it is board specific code, so put it here. */ pin_func = au_readl(SYS_PINFUNC); au_sync(); pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; au_writel(pin_func, SYS_PINFUNC); au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */ au_sync(); } #endif #if defined(CONFIG_I2C_AU1550) { u32 freq0, clksrc; u32 pin_func; /* Select SMBus in CPLD */ bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); pin_func = au_readl(SYS_PINFUNC); au_sync(); pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); /* Set GPIOs correctly */ pin_func |= 2 << 17; au_writel(pin_func, SYS_PINFUNC); au_sync(); /* The I2C driver depends on 50 MHz clock */ freq0 = au_readl(SYS_FREQCTRL0); au_sync(); freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); freq0 |= 3 << SYS_FC_FRDIV1_BIT; /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */ au_writel(freq0, SYS_FREQCTRL0); au_sync(); freq0 |= SYS_FC_FE1; au_writel(freq0, SYS_FREQCTRL0); au_sync(); clksrc = au_readl(SYS_CLKSRC); au_sync(); clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK); /* Bit 22 is EXTCLK0 for PSC0 */ clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT; au_writel(clksrc, SYS_CLKSRC); au_sync(); } #endif /* * The Pb1200 development board uses external MUX for PSC0 to * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI */ #ifdef CONFIG_I2C_AU1550 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); #endif au_sync(); }
int __init db1200_dev_setup(void) { unsigned long pfc; unsigned short sw; int swapped, bid; struct clk *c; bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); if ((bid == BCSR_WHOAMI_PB1200_DDR1) || (bid == BCSR_WHOAMI_PB1200_DDR2)) { if (pb1200_res_fixup()) return -ENODEV; } /* GPIO7 is low-level triggered CPLD cascade */ irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW); bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); /* SMBus/SPI on PSC0, Audio on PSC1 */ pfc = alchemy_rdsys(AU1000_SYS_PINFUNC); pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); /* get 50MHz for I2C driver on PSC0 */ c = clk_get(NULL, "psc0_intclk"); if (!IS_ERR(c)) { pfc = clk_round_rate(c, 50000000); if ((pfc < 1) || (abs(50000000 - pfc) > 2500000)) pr_warn("DB1200: cant get I2C close to 50MHz\n"); else clk_set_rate(c, pfc); clk_put(c); } /* insert/eject pairs: one of both is always screaming. To avoid * issues they must not be automatically enabled when initially * requested. */ irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); i2c_register_board_info(0, db1200_i2c_devs, ARRAY_SIZE(db1200_i2c_devs)); spi_register_board_info(db1200_spi_devs, ARRAY_SIZE(db1200_i2c_devs)); /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) * or S12 on the PB1200. */ /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however * this pin is claimed by PSC0 (unused though, but pinmux doesn't * allow to free it without crippling the SPI interface). * As a result, in SPI mode, OTG simply won't work (PSC0 uses * it as an input pin which is pulled high on the boards). */ pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A; /* switch off OTG VBUS supply */ gpio_request(215, "otg-vbus"); gpio_direction_output(215, 1); printk(KERN_INFO "%s device configuration:\n", get_system_type()); sw = bcsr_read(BCSR_SWITCHES); if (sw & BCSR_SWITCHES_DIP_8) { db1200_devs[0] = &db1200_i2c_dev; bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */ printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n"); printk(KERN_INFO " OTG port VBUS supply available!\n"); } else { db1200_devs[0] = &db1200_spi_dev; bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX); pfc |= (1 << 17); /* PSC0 owns GPIO215 */ printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n"); printk(KERN_INFO " OTG port VBUS supply disabled\n"); } alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S! * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S */ sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7; if (sw == BCSR_SWITCHES_DIP_8) { bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX); db1200_audio_dev.name = "au1xpsc_i2s"; db1200_sound_dev.name = "db1200-i2s"; printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n"); } else { bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0); db1200_audio_dev.name = "au1xpsc_ac97"; db1200_sound_dev.name = "db1200-ac97"; printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n"); } /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ c = clk_get(NULL, "psc1_intclk"); if (!IS_ERR(c)) { clk_prepare_enable(c); clk_put(c); } __raw_writel(PSC_SEL_CLK_SERCLK, (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR, AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, AU1000_PCMCIA_MEM_PHYS_ADDR, AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, AU1000_PCMCIA_IO_PHYS_ADDR, AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, DB1200_PC0_INT, DB1200_PC0_INSERT_INT, /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0); db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, DB1200_PC1_INT, DB1200_PC1_INSERT_INT, /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1); swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; db1x_register_norflash(64 << 20, 2, swapped); platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */ if ((bid == BCSR_WHOAMI_PB1200_DDR1) || (bid == BCSR_WHOAMI_PB1200_DDR2)) platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs)); return 0; }
static int __init db1200_dev_init(void) { unsigned long pfc; unsigned short sw; int swapped; i2c_register_board_info(0, db1200_i2c_devs, ARRAY_SIZE(db1200_i2c_devs)); spi_register_board_info(db1200_spi_devs, ARRAY_SIZE(db1200_i2c_devs)); /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) */ /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however * this pin is claimed by PSC0 (unused though, but pinmux doesn't * allow to free it without crippling the SPI interface). * As a result, in SPI mode, OTG simply won't work (PSC0 uses * it as an input pin which is pulled high on the boards). */ pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A; /* switch off OTG VBUS supply */ gpio_request(215, "otg-vbus"); gpio_direction_output(215, 1); printk(KERN_INFO "DB1200 device configuration:\n"); sw = bcsr_read(BCSR_SWITCHES); if (sw & BCSR_SWITCHES_DIP_8) { db1200_devs[0] = &db1200_i2c_dev; bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */ printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n"); printk(KERN_INFO " OTG port VBUS supply available!\n"); } else { db1200_devs[0] = &db1200_spi_dev; bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX); pfc |= (1 << 17); /* PSC0 owns GPIO215 */ printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n"); printk(KERN_INFO " OTG port VBUS supply disabled\n"); } __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); wmb(); /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S! * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S */ sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7; if (sw == BCSR_SWITCHES_DIP_8) { bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX); db1200_audio_dev.name = "au1xpsc_i2s"; db1200_sound_dev.name = "db1200-i2s"; printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n"); } else { bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0); db1200_audio_dev.name = "au1xpsc_ac97"; db1200_sound_dev.name = "db1200-ac97"; printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n"); } /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ __raw_writel(PSC_SEL_CLK_SERCLK, (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR, AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, AU1000_PCMCIA_MEM_PHYS_ADDR, AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, AU1000_PCMCIA_IO_PHYS_ADDR, AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, DB1200_PC0_INT, DB1200_PC0_INSERT_INT, /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0); db1x_register_pcmcia_socket( AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, DB1200_PC1_INT, DB1200_PC1_INSERT_INT, /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1); swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; db1x_register_norflash(64 << 20, 2, swapped); return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); }
static int au1k_irda_net_init(struct net_device *dev) { struct au1k_private *aup = netdev_priv(dev); int i, retval = 0, err; db_dest_t *pDB, *pDBfree; dma_addr_t temp; err = au1k_irda_init_iobuf(&aup->rx_buff, 14384); if (err) goto out1; dev->netdev_ops = &au1k_irda_netdev_ops; irda_init_max_qos_capabilies(&aup->qos); /* The only value we must override it the baudrate */ aup->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| IR_115200|IR_576000 |(IR_4000000 << 8); aup->qos.min_turn_time.bits = qos_mtt_bits; irda_qos_bits_to_value(&aup->qos); retval = -ENOMEM; /* Tx ring follows rx ring + 512 bytes */ /* we need a 1k aligned buffer */ aup->rx_ring[0] = (ring_dest_t *) dma_alloc(2*MAX_NUM_IR_DESC*(sizeof(ring_dest_t)), &temp); if (!aup->rx_ring[0]) goto out2; /* allocate the data buffers */ aup->db[0].vaddr = (void *)dma_alloc(MAX_BUF_SIZE * 2*NUM_IR_DESC, &temp); if (!aup->db[0].vaddr) goto out3; setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512); pDBfree = NULL; pDB = aup->db; for (i=0; i<(2*NUM_IR_DESC); i++) { pDB->pnext = pDBfree; pDBfree = pDB; pDB->vaddr = (u32 *)((unsigned)aup->db[0].vaddr + MAX_BUF_SIZE*i); pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); pDB++; } aup->pDBfree = pDBfree; /* attach a data buffer to each descriptor */ for (i=0; i<NUM_IR_DESC; i++) { pDB = GetFreeDB(aup); if (!pDB) goto out; aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); aup->rx_db_inuse[i] = pDB; } for (i=0; i<NUM_IR_DESC; i++) { pDB = GetFreeDB(aup); if (!pDB) goto out; aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); aup->tx_ring[i]->count_0 = 0; aup->tx_ring[i]->count_1 = 0; aup->tx_ring[i]->flags = 0; aup->tx_db_inuse[i] = pDB; } #if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) /* power on */ bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, BCSR_RESETS_IRDA_MODE_FULL); #endif return 0; out3: dma_free((void *)aup->rx_ring[0], 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); out2: kfree(aup->rx_buff.head); out1: printk(KERN_ERR "au1k_init_module failed. Returns %d\n", retval); return retval; }