void init() {
// In case disabled by boot-loader
__enable_irq();
initPorts();
initTimers();
bdm_interfaceOff();
initUSB();
#ifdef VDD_ON_INITIALLY
// For compatibility with original board s/w
// The board is powered when initially plugged in
#if (VDD_ON_INITIALLY == 3)
bdm_option.targetVdd = BDM_TARGET_VDD_3V3;
#elif (VDD_ON_INITIALLY == 5)
bdm_option.targetVdd = BDM_TARGET_VDD_5;
#else
bdm_option.targetVdd = BDM_TARGET_VDD_OFF;
#endif
bdm_setTargetVdd();
RESET_LOW();
WAIT_MS(100);
RESET_3STATE();
#endif
}
//! Cycle power ON to target
//!
//! @param mode
//! - \ref RESET_SPECIAL => Power on in special mode,
//! - \ref RESET_NORMAL => Power on in normal mode
//!
//! BKGD/BKPT is held low when power is re-applied to start
//! target with BDM active if RESET_SPECIAL
//!
//! @return
//! \ref BDM_RC_OK => Target Vdd confirmed on target \n
//! \ref BDM_RC_VDD_WRONG_MODE => Target Vdd not controlled by BDM interface \n
//! \ref BDM_RC_VDD_NOT_PRESENT => Target Vdd failed to rise \n
//! \ref BDM_RC_RESET_TIMEOUT_RISE => RESET signal failed to rise \n
//! \ref BDM_RC_BKGD_TIMEOUT => BKGD signal failed to rise
//!
uint8_t bdm_cycleTargetVddOn(uint8_t mode) {
uint8_t rc = BDM_RC_OK;
mode &= RESET_MODE_MASK;
#if (HW_CAPABILITY&CAP_VDDCONTROL)
switch(cable_status.target_type) {
#if (HW_CAPABILITY&CAP_CFVx_HW)
case T_CFVx:
bdmcf_interfaceIdle(); // Make sure BDM interface is idle
if (mode == RESET_SPECIAL)
BKPT_LOW();
break;
#endif
#if (HW_CAPABILITY&CAP_BDM)
case T_HC12:
case T_HCS08:
case T_RS08:
case T_CFV1:
bdmHCS_interfaceIdle(); // Make sure BDM interface is idle
if (mode == RESET_SPECIAL) {
BDM_LOW(); // BKGD pin=L
}
break;
#endif
#if (HW_CAPABILITY&CAP_JTAG_HW)
case T_JTAG:
case T_MC56F80xx:
case T_ARM_JTAG:
jtag_interfaceIdle(); // Make sure BDM interface is idle
#endif
break;
default:
swd_interfaceIdle();
break;
}
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 0;
DEBUG_PIN = 1;
DEBUG_PIN = 0;
DEBUG_PIN = 1;
#endif // (DEBUG&CYCLE_DEBUG)
// Power on with TargetVdd monitoring off
rc = bdm_setTargetVdd();
if (rc != BDM_RC_OK) // No target Vdd
goto cleanUp;
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 1;
DEBUG_PIN = 0;
#endif // (DEBUG&CYCLE_DEBUG)
#if (HW_CAPABILITY&CAP_RST_IN)
// RESET rise may be delayed by target POR
if (bdm_option.useResetSignal) {
WAIT_WITH_TIMEOUT_S( 2 /* s */, (RESET_IN!=0) );
}
#endif
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 0;
DEBUG_PIN = 1;
#endif // (DEBUG&CYCLE_DEBUG)
// Let signals settle & CPU to finish reset (with BKGD held low)
WAIT_US(BKGD_WAITus);
#if (HW_CAPABILITY&CAP_RST_IN)
if (bdm_option.useResetSignal && (RESET_IN==0)) {
// RESET didn't rise
rc = BDM_RC_RESET_TIMEOUT_RISE;
goto cleanUp;
}
#endif //(HW_CAPABILITY&CAP_RST_IO)
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 1;
DEBUG_PIN = 0;
#endif // (DEBUG&CYCLE_DEBUG)
#if (HW_CAPABILITY&CAP_CFVx_HW)
if (cable_status.target_type == T_CFVx)
bdmcf_interfaceIdle(); // Release BKPT etc
else
#endif
#if (HW_CAPABILITY&CAP_BDM)
bdmHCS_interfaceIdle(); // Release BKGD
#endif
// Let processor start up
WAIT_MS(RESET_RECOVERYms);
#if 0
// Removed - some targets may be holding BKGD low (e.g. used as port pin)
// This situation is handled elsewhere (requires power cycle)
if (BDM_IN==0) { // BKGD didn't rise!
rc = BDM_RC_BKGD_TIMEOUT;
goto cleanUp;
}
#endif // 0
cable_status.reset = RESET_DETECTED; // Cycling the power should have reset it!
cleanUp:
#if (HW_CAPABILITY&CAP_CFVx_HW)
if (cable_status.target_type == T_CFVx)
bdmcf_interfaceIdle(); // Release BKPT etc
else
#endif
#if (HW_CAPABILITY&CAP_BDM)
bdmHCS_interfaceIdle(); // Release BKGD
#endif
WAIT_MS( 250 /* ms */);
// EnableInterrupts;
#endif // CAP_VDDCONTROL
(void)bdm_checkTargetVdd(); // Update Target Vdd LED & power status
return(rc);
}
/*! \brief Initialise the system.
*
* Initialisation of the following:
* \li Default port values
* \li Watchdog (off),
* \li Stack,
* \li BDM interface,
* \li USB interface.
* \li Configure Clock for 48MHz operation
*/
static void init(void) {
// Default ports to inputs
PTADD = 0x00;
PTBDD = 0x00;
#if (CPU==JMxx)
PTCDD = 0x00;
PTDDD = 0x00;
PTEDD = 0x00;
PTFDD = 0x00;
PTGDD = 0x00;
#endif
// Turn off important things
#if ((HW_CAPABILITY & CAP_FLASH) != 0)
(void)bdmSetVpp(BDM_TARGET_VPP_OFF);
#endif
VDD_OFF();
// Default to Ports have PUPs
// Note - this doesn't affect outputs
PTAPE = 0xFF;
PTBPE = 0xFF;
#if (CPU==JMxx)
PTCPE = 0xFF;
PTDPE = 0xFF;
PTEPE = 0xFF;
PTFPE = 0xFF;
PTGPE = 0xFF;
#endif
EnableInterrupts;
#ifndef SOPT1_BKGDPE_MASK
#define SOPT1_BKGDPE_MASK (0)
#endif
SOPT1 = SOPT1_STOPE_MASK|SOPT1_BKGDPE_MASK; // Disable COP, enable STOP instr. & BKGD pin
#if (HW_CAPABILITY&CAP_VDDSENSE)
SPMSC1_BGBE = 1; // Enable Bandgap Reference
#endif
LED_INIT();
clearStack();
initUSB(); // Assumes clock already done
(void)bdm_init();
(void)bdm_off();
#ifdef VDD_ON_INITIALLY
// For compatibility with original board s/w
// The board is powered when initially plugged in
#if (VDD_ON_INITIALLY == 3)
bdm_option.targetVdd = BDM_TARGET_VDD_3V3;
#elif (VDD_ON_INITIALLY == 5)
bdm_option.targetVdd = BDM_TARGET_VDD_5;
#else
#error "Illegal VDD_ON_INITIALLY value"
#endif
(void)bdm_interfaceOff();
(void)bdm_setTargetVdd();
#endif
#if (DEBUG&SCI_DEBUG) != 0)
debugSCIInit();
#endif
}
