//! Target power has been externally cycled. Holds BKPT/BKGD low while Vdd rises
//!
//! @return
//! \ref BDM_RC_OK => Success \n
//! \ref BDM_RC_VDD_NOT_PRESENT => various errors
//
U8 bdmCF_powerOnReset(void) {
U8 rc = 0;
#if (HW_CAPABILITY&CAP_VDDSENSE)
bdmcf_interfaceIdle(); // Make sure BDM interface is idle
BKPT_LOW();
// Wait for Vdd to rise within 50% of 3V and RESET to return high
// RESET rise may be delayed by target POR
WAIT_WITH_TIMEOUT_MS( 250 /* ms */, (bdm_targetVddMeasure()>75)&&
(!bdm_option.useResetSignal)||RESET_IS_HIGH);
// Let signals settle & CPU to finish reset (with BKGD held low)
WAIT_MS(BKGD_WAITus);
if (bdm_targetVddMeasure()<=70) // Vpp didn't turn on!
rc = BDM_RC_VDD_NOT_PRESENT;
if (bdm_option.useResetSignal && (!RESET_IS_HIGH)) // RESET didn't rise
rc = BDM_RC_RESET_TIMEOUT_RISE;
bdmcf_interfaceIdle(); // Make sure BDM interface is idle (BKGD now high)
// Let signals settle
WAIT_MS(RESET_SETTLEms);
cable_status.reset = RESET_DETECTED; // Record the fact that reset was asserted
#endif // (HW_CAPABILITY&CAP_VDDSENSE)
return(rc);
}
//! Cycle power OFF to target
//!
//! @return
//! \ref BDM_RC_OK => No error \n
//! \ref BDM_RC_VDD_WRONG_MODE => Target Vdd not controlled by BDM interface \n
//! \ref BDM_RC_VDD_NOT_REMOVED => Target Vdd failed to fall \n
//!
uint8_t bdm_cycleTargetVddOff(void) {
uint8_t rc = BDM_RC_OK;
#if (HW_CAPABILITY&CAP_VDDCONTROL)
(void)bdm_checkTargetVdd();
if (bdm_option.targetVdd == BDM_TARGET_VDD_OFF)
return BDM_RC_VDD_WRONG_MODE;
#if (HW_CAPABILITY&CAP_CFVx_HW)
if (cable_status.target_type == T_CFVx)
bdmcf_interfaceIdle(); // Make sure BDM interface is idle
else
#endif
{
#if (HW_CAPABILITY&CAP_BDM)
bdmHCS_interfaceIdle(); // Make sure BDM interface is idle
#endif
}
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 0;
DEBUG_PIN = 1;
#endif
// Power off & wait for Vdd to fall to ~5%
VDD_OFF();
WAIT_WITH_TIMEOUT_S( 5 /* s */, (bdm_targetVddMeasure()<10) );
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 1;
DEBUG_PIN = 0;
#endif
if (bdm_targetVddMeasure()>=15) // Vdd didn't turn off!
rc = BDM_RC_VDD_NOT_REMOVED;
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 0;
DEBUG_PIN = 1;
#endif
(void)bdm_checkTargetVdd(); // Update Target Vdd LED
// Wait a while with power off
WAIT_US(RESET_SETTLEms);
// Clear Vdd monitoring interrupt
#if (HW_CAPABILITY&CAP_VDDSENSE)
CLEAR_VDD_SENSE_FLAG(); // Clear Vdd monitoring flag
#endif
(void)bdm_checkTargetVdd(); // Update Target Vdd LED
#endif // CAP_VDDCONTROL
return(rc);
}
//! Initialises the CF BDM interface to default state (including speed)
//!
void bdmcf_init(void) {
DSI_OUT_PER = 1;
DSCLK_OUT_PER = 1;
#ifdef DSCLK_DRV_PER
DSCLK_DRV_PER = 1; // Holds DSCLK driver disabled when unused
#endif
BKPT_OUT_PER = 1; // Holds BKPT_OUT inactive when unused
#ifdef TA_OUT_PER
TA_OUT_PER = 1; // Holds TA_OUT inactive when unused
#endif
RESET_IN_PER = 1; // Needed for input level translation to 5V
RESET_OUT_PER = 1; // Holds RESET_OUT inactive when unused
#ifdef ALLPST_IN_PER
ALLPST_IN_PER = 1; // Needed for input level translation to 5V
#endif
#ifdef PST_IN_ENABLE
PST_IN_ENABLE(); // OSBDM boards
#endif
// Set up inputs
DSO_IN_DDR = 0;
RESET_IN_DDR = 0;
#ifdef ALLPST_IN_DDR
ALLPST_IN_DDR = 0;
#endif
DSCLK_DRV_ENABLE(); // DSCLK is driven
#ifdef SPI2C1
SPI2C1 = SPIxC1_OFF; // SPI2 is unused (Port pin is used for BKPT*)
#endif
(void)spi_setSpeed(0);
SPIxC2 = SPIxC2_16; // Initialise SPI1 but leave disabled
bdmcf_interfaceIdle();
#ifdef TCLK_CTL_DISABLE
TCLK_CTL_DISABLE();
#endif
}
//! Turns off the BDM interface
//!
//! Depending upon settings, may leave target power on.
//!
void bdmCF_off( void ) {
bdmcf_interfaceIdle();
TRST_3STATE();
}
//! Sets the BDM interface to a suspended state
//!
//! - All signals idle \n
//! - All voltages off.
//!
void bdmCF_suspend(void) {
VDD_OFF();
bdmcf_interfaceIdle();
}
//! Cycle power ON to target
//!
//! @param mode
//! - \ref RESET_SPECIAL => Power on in special mode,
//! - \ref RESET_NORMAL => Power on in normal mode
//!
//! BKGD/BKPT is held low when power is re-applied to start
//! target with BDM active if RESET_SPECIAL
//!
//! @return
//! \ref BDM_RC_OK => Target Vdd confirmed on target \n
//! \ref BDM_RC_VDD_WRONG_MODE => Target Vdd not controlled by BDM interface \n
//! \ref BDM_RC_VDD_NOT_PRESENT => Target Vdd failed to rise \n
//! \ref BDM_RC_RESET_TIMEOUT_RISE => RESET signal failed to rise \n
//! \ref BDM_RC_BKGD_TIMEOUT => BKGD signal failed to rise
//!
uint8_t bdm_cycleTargetVddOn(uint8_t mode) {
uint8_t rc = BDM_RC_OK;
mode &= RESET_MODE_MASK;
#if (HW_CAPABILITY&CAP_VDDCONTROL)
switch(cable_status.target_type) {
#if (HW_CAPABILITY&CAP_CFVx_HW)
case T_CFVx:
bdmcf_interfaceIdle(); // Make sure BDM interface is idle
if (mode == RESET_SPECIAL)
BKPT_LOW();
break;
#endif
#if (HW_CAPABILITY&CAP_BDM)
case T_HC12:
case T_HCS08:
case T_RS08:
case T_CFV1:
bdmHCS_interfaceIdle(); // Make sure BDM interface is idle
if (mode == RESET_SPECIAL) {
BDM_LOW(); // BKGD pin=L
}
break;
#endif
#if (HW_CAPABILITY&CAP_JTAG_HW)
case T_JTAG:
case T_MC56F80xx:
case T_ARM_JTAG:
jtag_interfaceIdle(); // Make sure BDM interface is idle
#endif
break;
default:
swd_interfaceIdle();
break;
}
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 0;
DEBUG_PIN = 1;
DEBUG_PIN = 0;
DEBUG_PIN = 1;
#endif // (DEBUG&CYCLE_DEBUG)
// Power on with TargetVdd monitoring off
rc = bdm_setTargetVdd();
if (rc != BDM_RC_OK) // No target Vdd
goto cleanUp;
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 1;
DEBUG_PIN = 0;
#endif // (DEBUG&CYCLE_DEBUG)
#if (HW_CAPABILITY&CAP_RST_IN)
// RESET rise may be delayed by target POR
if (bdm_option.useResetSignal) {
WAIT_WITH_TIMEOUT_S( 2 /* s */, (RESET_IN!=0) );
}
#endif
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 0;
DEBUG_PIN = 1;
#endif // (DEBUG&CYCLE_DEBUG)
// Let signals settle & CPU to finish reset (with BKGD held low)
WAIT_US(BKGD_WAITus);
#if (HW_CAPABILITY&CAP_RST_IN)
if (bdm_option.useResetSignal && (RESET_IN==0)) {
// RESET didn't rise
rc = BDM_RC_RESET_TIMEOUT_RISE;
goto cleanUp;
}
#endif //(HW_CAPABILITY&CAP_RST_IO)
#if (DEBUG&CYCLE_DEBUG)
DEBUG_PIN = 1;
DEBUG_PIN = 0;
#endif // (DEBUG&CYCLE_DEBUG)
#if (HW_CAPABILITY&CAP_CFVx_HW)
if (cable_status.target_type == T_CFVx)
bdmcf_interfaceIdle(); // Release BKPT etc
else
#endif
#if (HW_CAPABILITY&CAP_BDM)
bdmHCS_interfaceIdle(); // Release BKGD
#endif
// Let processor start up
WAIT_MS(RESET_RECOVERYms);
#if 0
// Removed - some targets may be holding BKGD low (e.g. used as port pin)
// This situation is handled elsewhere (requires power cycle)
if (BDM_IN==0) { // BKGD didn't rise!
rc = BDM_RC_BKGD_TIMEOUT;
goto cleanUp;
}
#endif // 0
cable_status.reset = RESET_DETECTED; // Cycling the power should have reset it!
cleanUp:
#if (HW_CAPABILITY&CAP_CFVx_HW)
if (cable_status.target_type == T_CFVx)
bdmcf_interfaceIdle(); // Release BKPT etc
else
#endif
#if (HW_CAPABILITY&CAP_BDM)
bdmHCS_interfaceIdle(); // Release BKGD
#endif
WAIT_MS( 250 /* ms */);
// EnableInterrupts;
#endif // CAP_VDDCONTROL
(void)bdm_checkTargetVdd(); // Update Target Vdd LED & power status
return(rc);
}
//! Turns off the BDM interface
//!
//! Depending upon settings, may leave target power on.
//!
void bdmCF_off( void ) {
bdmcf_interfaceIdle();
#ifdef TRST_3STATE
TRST_3STATE();
#endif
}
