void __led_init(led_id_t mask, int state)
{
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~(PF8));
bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~(PG11 | PG12));
bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() & ~(PF8));
bfin_write_PORTGIO_INEN(bfin_read_PORTGIO_INEN() & ~(PG11 | PG12));
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (PF8));
bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | (PG11 | PG12));
}
int post_key_pressed(void)
{
int i, n;
unsigned short value;
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF5);
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~PF5);
bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | PF5);
SSYNC();
post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
for (i = 0; i < KEY_LOOP; i++) {
value = bfin_read_PORTFIO() & PF5;
if (bfin_read_UART0_RBR() == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0)
goto key_pressed;
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
post_out_buff("\b2\0");
for (i = 0; i < KEY_LOOP; i++) {
value = bfin_read_PORTFIO() & PF5;
if (bfin_read_UART0_RBR() == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0)
goto key_pressed;
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
post_out_buff("\b1\0");
for (i = 0; i < KEY_LOOP; i++) {
value = bfin_read_PORTFIO() & PF5;
if (bfin_read_UART0_RBR() == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0)
goto key_pressed;
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
key_pressed:
post_out_buff("\b0");
post_out_buff("\n\r\0");
if (value == 0)
return 0;
post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
return 1;
}
void bfspi_reset(int reset_bit) {
PRINTK("toggle reset\n");
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
PRINTK("set reset to PF%d\n",reset_bit);
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (1<<reset_bit));
__builtin_bfin_ssync();
bfin_write_FIO_FLAG_C((1<<reset_bit));
__builtin_bfin_ssync();
udelay(100);
bfin_write_FIO_FLAG_S((1<<reset_bit));
__builtin_bfin_ssync();
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
if (reset_bit == 1) {
PRINTK("set reset to PF10\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFBFF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0400);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<10);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<10);
__builtin_bfin_ssync();
} else if (reset_bit == 2) {
PRINTK("Error: cannot set reset to PJ11\n");
} else if (reset_bit == 3) {
PRINTK("Error: cannot set reset to PJ10\n");
} else if (reset_bit == 4) {
PRINTK("set reset to PF6\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFFBF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0040);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<6);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<6);
__builtin_bfin_ssync();
} else if (reset_bit == 5) {
PRINTK("set reset to PF5\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFFDF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0020);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<5);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<5);
__builtin_bfin_ssync();
} else if (reset_bit == 6) {
PRINTK("set reset to PF4\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFFEF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0010);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<4);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<4);
__builtin_bfin_ssync();
} else if (reset_bit == 7) {
PRINTK("Error: cannot set reset to PJ5\n");
} else if (reset_bit == 8) {
PRINTK("Using PF8 for reset...\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFEFF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0100);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<8);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<8);
} else if ( reset_bit == 9 ) {
PRINTK("Using PF9 for reset...\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFDFF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0200);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<9);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<9);
}
#endif
/*
p24 3050 data sheet, allow 1ms for PLL lock, with
less than 1ms (1000us) I found register 2 would have
a value of 0 rather than 3, indicating a bad reset.
*/
udelay(1000);
}
void bfspi_hardware_init(int baud, u16 new_chip_select_mask)
{
u16 ctl_reg, flag;
int cs, bit;
if (baud < 4) {
printk("\nkern>>baud = %d may mean SPI clock too fast for Si labs 3050"
"consider baud == 4 or greater", baud);
}
PRINTK("\nkern>> bfspi_spi_init\n");
PRINTK("kern>> new_chip_select_mask = 0x%04x\n", new_chip_select_mask);
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
PRINTK("kern>> FIOD_DIR = 0x%04x\n", bfin_read_FIO_DIR());
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
PRINTK(" FIOD_DIR = 0x%04x\n", bfin_read_PORTFIO_DIR());
#endif
/* grab SPISEL/GPIO pins for SPI, keep level of SPISEL pins H */
chip_select_mask |= new_chip_select_mask;
flag = 0xff00 | (chip_select_mask & 0xff);
/* set up chip selects greater than PF7 */
if (chip_select_mask & 0xff00) {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (chip_select_mask & 0xff00));
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (chip_select_mask & 0xff00));
#endif
__builtin_bfin_ssync();
}
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
PRINTK("kern>> After FIOD_DIR = 0x%04x\n", bfin_read_FIO_DIR());
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
PRINTK(" After FIOD_DIR = 0x%04x\n",bfin_read_PORTFIO_DIR());
/* we need to work thru each bit in mask and set the MUX regs */
for(bit=0; bit<8; bit++) {
if (chip_select_mask & (1<<bit)) {
PRINTK("SPI CS bit: %d enabled\n", bit);
cs = bit;
if (cs == 1) {
PRINTK("set for chip select 1\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);
__builtin_bfin_ssync();
} else if (cs == 2 || cs == 3) {
PRINTK("set for chip select 2\n");
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
__builtin_bfin_ssync();
} else if (cs == 4) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840);
__builtin_bfin_ssync();
} else if (cs == 5) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820);
__builtin_bfin_ssync();
} else if (cs == 6) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810);
__builtin_bfin_ssync();
} else if (cs == 7) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
__builtin_bfin_ssync();
}
}
}
#endif
/* note TIMOD = 00 - reading SPI_RDBR kicks off transfer */
//Undefines flags lets patch it for now. BFSI is kind of obsolate.
//Will be replaced in teh future
ctl_reg = 0xD004; //0101 1100 0000 0100 SPE | MSTR | CPOL | CPHA | SZ;
ctl_reg |= (spimode << 10);
bfin_write_SPI_FLG(flag);
bfin_write_SPI_BAUD(baud);
bfin_write_SPI_CTL(ctl_reg);
}
