void blackfin_invalidate_entire_dcache(void) { u32 dmem = bfin_read_DMEM_CONTROL(); bfin_write_DMEM_CONTROL(dmem & ~0xc); SSYNC(); bfin_write_DMEM_CONTROL(dmem); SSYNC(); }
void bfin_dcache_init(void) { unsigned long *table = dcplb_table; unsigned long ctrl; int i; for (i = 0; i < MAX_CPLBS; i++) { unsigned long addr = *table++; unsigned long data = *table++; if (addr == (unsigned long)-1) break; bfin_write32(DCPLB_ADDR0 + i * 4, addr); bfin_write32(DCPLB_DATA0 + i * 4, data); } ctrl = bfin_read_DMEM_CONTROL(); ctrl |= DMEM_CNTR; bfin_write_DMEM_CONTROL(ctrl); }
void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) { unsigned long ctrl; int i; for (i = 0; i < MAX_CPLBS; i++) { bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr); bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data); } ctrl = bfin_read_DMEM_CONTROL(); /* * Anomaly notes: * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL * register, so that the port preferences for DAG0 and DAG1 are set * to port B */ ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0); /* CSYNC to ensure load store ordering */ CSYNC(); bfin_write_DMEM_CONTROL(ctrl); SSYNC(); }
void dcache_disable(void) { bfin_write_DMEM_CONTROL(0); SSYNC(); }
void dcache_enable(void) { bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); SSYNC(); }