int irq_init(void) { #ifdef SIC_IMASK0 bfin_write_SIC_IMASK0(0); bfin_write_SIC_IMASK1(0); # ifdef SIC_IMASK2 bfin_write_SIC_IMASK2(0); # endif #elif defined(SICA_IMASK0) bfin_write_SICA_IMASK0(0); bfin_write_SICA_IMASK1(0); #elif defined(SIC_IMASK) bfin_write_SIC_IMASK(0); #endif /* Set up a dummy NMI handler if needed. */ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219) bfin_write_EVT2(evt_nmi); /* NMI */ bfin_write_EVT5(evt_default); /* hardware error */ bfin_write_EVT6(evt_default); /* core timer */ bfin_write_EVT7(evt_default); bfin_write_EVT8(evt_default); bfin_write_EVT9(evt_default); bfin_write_EVT10(evt_default); bfin_write_EVT11(evt_default); bfin_write_EVT12(evt_default); bfin_write_EVT13(evt_default); bfin_write_EVT14(evt_default); bfin_write_EVT15(evt_default); bfin_write_ILAT(0); CSYNC(); /* enable hardware error irq */ irq_flags = 0x3f; local_irq_enable(); return 0; }
int irq_init(void) { #ifdef SIC_IMASK0 bfin_write_SIC_IMASK0(0); bfin_write_SIC_IMASK1(0); # ifdef SIC_IMASK2 bfin_write_SIC_IMASK2(0); # endif #elif defined(SICA_IMASK0) bfin_write_SICA_IMASK0(0); bfin_write_SICA_IMASK1(0); #else bfin_write_SIC_IMASK(0); #endif bfin_write_EVT2(evt_default); /* NMI */ bfin_write_EVT5(evt_default); /* hardware error */ bfin_write_EVT6(evt_default); /* core timer */ bfin_write_EVT7(evt_default); bfin_write_EVT8(evt_default); bfin_write_EVT9(evt_default); bfin_write_EVT10(evt_default); bfin_write_EVT11(evt_default); bfin_write_EVT12(evt_default); bfin_write_EVT13(evt_default); bfin_write_EVT14(evt_default); bfin_write_EVT15(evt_default); bfin_write_ILAT(0); CSYNC(); return 0; }