void bfspi_hardware_init(int baud, u16 new_chip_select_mask)
{
u16 ctl_reg, flag;
int cs, bit;
if (baud < 4) {
printk("\nkern>>baud = %d may mean SPI clock too fast for Si labs 3050"
"consider baud == 4 or greater", baud);
}
PRINTK("\nkern>> bfspi_spi_init\n");
PRINTK("kern>> new_chip_select_mask = 0x%04x\n", new_chip_select_mask);
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
PRINTK("kern>> FIOD_DIR = 0x%04x\n", bfin_read_FIO_DIR());
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
PRINTK(" FIOD_DIR = 0x%04x\n", bfin_read_PORTFIO_DIR());
#endif
/* grab SPISEL/GPIO pins for SPI, keep level of SPISEL pins H */
chip_select_mask |= new_chip_select_mask;
flag = 0xff00 | (chip_select_mask & 0xff);
/* set up chip selects greater than PF7 */
if (chip_select_mask & 0xff00) {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (chip_select_mask & 0xff00));
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (chip_select_mask & 0xff00));
#endif
__builtin_bfin_ssync();
}
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
PRINTK("kern>> After FIOD_DIR = 0x%04x\n", bfin_read_FIO_DIR());
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
PRINTK(" After FIOD_DIR = 0x%04x\n",bfin_read_PORTFIO_DIR());
/* we need to work thru each bit in mask and set the MUX regs */
for(bit=0; bit<8; bit++) {
if (chip_select_mask & (1<<bit)) {
PRINTK("SPI CS bit: %d enabled\n", bit);
cs = bit;
if (cs == 1) {
PRINTK("set for chip select 1\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);
__builtin_bfin_ssync();
} else if (cs == 2 || cs == 3) {
PRINTK("set for chip select 2\n");
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
__builtin_bfin_ssync();
} else if (cs == 4) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840);
__builtin_bfin_ssync();
} else if (cs == 5) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820);
__builtin_bfin_ssync();
} else if (cs == 6) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810);
__builtin_bfin_ssync();
} else if (cs == 7) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
__builtin_bfin_ssync();
}
}
}
#endif
/* note TIMOD = 00 - reading SPI_RDBR kicks off transfer */
//Undefines flags lets patch it for now. BFSI is kind of obsolate.
//Will be replaced in teh future
ctl_reg = 0xD004; //0101 1100 0000 0100 SPE | MSTR | CPOL | CPHA | SZ;
ctl_reg |= (spimode << 10);
bfin_write_SPI_FLG(flag);
bfin_write_SPI_BAUD(baud);
bfin_write_SPI_CTL(ctl_reg);
}
void __led_init(led_id_t mask, int state)
{
bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4));
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4));
}
