Esempio n. 1
0
void blackfin_invalidate_entire_icache(void)
{
	u32 imem = bfin_read_IMEM_CONTROL();
	bfin_write_IMEM_CONTROL(imem & ~0x4);
	SSYNC();
	bfin_write_IMEM_CONTROL(imem);
	SSYNC();
}
Esempio n. 2
0
void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
{
	unsigned long ctrl;
	int i;

	for (i = 0; i < MAX_CPLBS; i++) {
		bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
		bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
	}
	ctrl = bfin_read_IMEM_CONTROL();
	ctrl |= IMC | ENICPLB;
	/* CSYNC to ensure load store ordering */
	CSYNC();
	bfin_write_IMEM_CONTROL(ctrl);
	SSYNC();
}
Esempio n. 3
0
void bfin_icache_init(void)
{
	unsigned long *table = icplb_table;
	unsigned long ctrl;
	int i;

	for (i = 0; i < MAX_CPLBS; i++) {
		unsigned long addr = *table++;
		unsigned long data = *table++;
		if (addr == (unsigned long)-1)
			break;
		bfin_write32(ICPLB_ADDR0 + i * 4, addr);
		bfin_write32(ICPLB_DATA0 + i * 4, data);
	}
	ctrl = bfin_read_IMEM_CONTROL();
	ctrl |= IMC | ENICPLB;
	bfin_write_IMEM_CONTROL(ctrl);
}
Esempio n. 4
0
void icache_disable(void)
{
	bfin_write_IMEM_CONTROL(0);
	SSYNC();
}
Esempio n. 5
0
void icache_enable(void)
{
	bfin_write_IMEM_CONTROL(IMC | ENICPLB);
	SSYNC();
}