void sdram_init(void) { /* * EPOS EVM has 1GB LPDDR2 connected to EMIF. * GP EMV has 1GB DDR3 connected to EMIF * along with VTT regulator. */ if (board_is_eposevm()) { config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); } else if (board_is_evm_14_or_later()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz_production, 0); } else if (board_is_evm_12_or_later()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz_beta, 0); } else if (board_is_evm()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz, 0); } else if (board_is_sk()) { config_ddr(400, &ioregs_ddr3, NULL, NULL, &ddr3_sk_emif_regs_400Mhz, 0); } else if (board_is_idk()) { config_ddr(400, &ioregs_ddr3, NULL, NULL, &ddr3_idk_emif_regs_400Mhz, 0); } }
u32 rtc_only_get_board_type(void) { if (board_is_eposevm()) return RTC_BOARD_EPOS; else if (board_is_evm_14_or_later()) return RTC_BOARD_EVM14; else if (board_is_evm_12_or_later()) return RTC_BOARD_EVM12; else if (board_is_gpevm()) return RTC_BOARD_GPEVM; else if (board_is_sk()) return RTC_BOARD_SK; return 0; }
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) { if (board_is_eposevm()) { *regs = ext_phy_ctrl_const_base_lpddr2; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); } else if (board_is_evm_14_or_later()) { *regs = ext_phy_ctrl_const_base_ddr3_production; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production); } else if (board_is_evm_12_or_later()) { *regs = ext_phy_ctrl_const_base_ddr3_beta; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta); } else if (board_is_gpevm()) { *regs = ext_phy_ctrl_const_base_ddr3; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); } else if (board_is_sk()) { *regs = ext_phy_ctrl_const_base_ddr3_sk; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk); } return; }