void __init prom_init(void)
{
char *ptr;
cfe_init(cfe_handle, cfe_entry);
bchip_check_compat();
board_pinmux_setup();
bchip_mips_setup();
set_board_nmi_handler();
/* default to SATA (where available) or MTD rootfs */
#ifdef CONFIG_BRCM_HAS_SATA
ROOT_DEV = Root_SDA1;
#else
ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 0);
#endif
root_mountflags &= ~MS_RDONLY;
bchip_set_features();
#if defined(CONFIG_BRCM_IKOS_DEBUG)
strcpy(arcs_cmdline, "debug initcall_debug");
#elif !defined(CONFIG_BRCM_IKOS)
cfe_read_configuration();
#endif
brcm_setup_early_printk();
#ifdef CONFIG_CMDLINE_BOOL
#ifdef CONFIG_CMDLINE_OVERRIDE
strlcpy(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
#else
if (builtin_cmdline[0]) {
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
}
#endif
#endif
/* provide "ubiroot" alias to reduce typing */
if (strstr(arcs_cmdline, "ubiroot"))
strcat(arcs_cmdline, " ubi.mtd=rootfs rootfstype=ubifs "
"root=ubi0:rootfs");
ptr = strstr(arcs_cmdline, "memc1=");
if (ptr)
brcm_dram1_linux_mb = memparse(ptr + 6, &ptr) >> 20;
printk(KERN_INFO "Options: enet_en=%d enet0_mii=%d enet_no_mdio=%d "
"enet1_en=%d moca=%d\n",
brcm_enet_enabled, brcm_enet0_force_ext_mii,
brcm_enet_no_mdio, brcm_enet1_enabled, brcm_moca_enabled);
printk(KERN_INFO " sata=%d docsis=%d pci=%d pcie=%d smp=%d "
"usb=%d\n",
brcm_sata_enabled, brcm_docsis_platform, brcm_pci_enabled,
brcm_pcie_enabled, brcm_smp_enabled, brcm_usb_enabled);
bchip_early_setup();
board_get_ram_size(&brcm_dram0_size_mb, &brcm_dram1_size_mb);
do {
unsigned long dram0_mb = brcm_dram0_size_mb, mb;
mb = min(dram0_mb, BRCM_MAX_LOWER_MB);
dram0_mb -= mb;
add_memory_region(0, mb << 20, BOOT_MEM_RAM);
if (!dram0_mb)
break;
#ifdef CONFIG_BRCM_UPPER_MEMORY
mb = min(dram0_mb, BRCM_MAX_UPPER_MB);
dram0_mb -= mb;
brcm_upper_tlb_setup();
add_memory_region(UPPERMEM_START, mb << 20, BOOT_MEM_RAM);
if (!dram0_mb)
break;
#endif
#if defined(CONFIG_HIGHMEM)
add_memory_region(HIGHMEM_START, dram0_mb << 20, BOOT_MEM_RAM);
break;
#endif
/*
* We wound up here because the chip's architecture cannot
* make use of all MEMC0 RAM in Linux. i.e. no suitable
* HIGHMEM or upper memory options are supported by the CPU.
*
* But we can still report the excess memory as a "bonus"
* reserved (bmem) region, so the application can manage it.
*/
mb = brcm_dram0_size_mb - dram0_mb; /* Linux memory */
if (!brcm_dram1_size_mb && mb == 256) {
printk(KERN_INFO "MEMC0 split: %lu MB -> Linux; "
"%lu MB -> extra bmem\n", mb, dram0_mb);
brcm_dram1_size_mb = dram0_mb;
brcm_dram1_start = UPPERMEM_START;
}
} while (0);
#if defined(CONFIG_HIGHMEM) && defined(CONFIG_BRCM_HAS_1GB_MEMC1)
if (brcm_dram1_linux_mb > brcm_dram1_size_mb) {
printk(KERN_WARNING "warning: 'memc1=%luM' exceeds "
"available memory (%lu MB); ignoring\n",
brcm_dram1_linux_mb, brcm_dram1_size_mb);
brcm_dram1_linux_mb = 0;
} else if (brcm_dram1_linux_mb) {
/* Since the bootloader can only map the first 256M of memc1
* when it boots, if we get memc1= request from bootloader, we
* should try to pull the memory from the end to avoid crossing
* over the memory that is allocated for boot logo image by
* bootloader.
*/
unsigned long start_mb, start_b, size, splash_bound = 0;
if (0 == parse_splash_mem(arcs_cmdline, &splash_bound, &size)) {
splash_bound += size;
}
start_mb = brcm_dram1_size_mb - brcm_dram1_linux_mb;
start_b = start_mb << 20;
if (splash_bound > start_b) {
unsigned long orig_dram1 = brcm_dram1_linux_mb;
start_mb = (splash_bound + 0x000FFFFF) >> 20;
start_b = start_mb << 20;
brcm_dram1_linux_mb = brcm_dram1_size_mb - start_mb;
printk(KERN_WARNING "warning: 'memc1=%luM' starts "
" before splash memory bound (0x%lx);"
" adjusting to (memc1=%luM)\n",
orig_dram1, splash_bound, brcm_dram1_linux_mb);
}
printk(KERN_INFO "memc1: adding %luMB at %luMB "
"(0x%08lx@0x%08lx)",
brcm_dram1_linux_mb, (MEMC1_START >> 20) + start_mb,
brcm_dram1_linux_mb << 20, MEMC1_START + start_b);
add_memory_region(MEMC1_START + start_b,
brcm_dram1_linux_mb << 20,
BOOT_MEM_RAM);
}
void __init prom_init(void)
{
#ifdef CONFIG_MIPS_BRCM97XXX
int hasCfeParms = 0;
int res = -1;
char msg[COMMAND_LINE_SIZE];
extern void determineBootFromFlashOrRom(void);
#endif
uart_init(27000000);
/* jipeng - mask out UPG L2 interrupt here */
BDEV_WR(BCHP_IRQ0_IRQEN, 0);
#ifdef CONFIG_TIVO_KONTIKI
board_pinmux_setup();
#endif
/* Fill in platform information */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BRCM_STB;
#ifdef BRCM_SATA_SUPPORTED
brcm_sata_enabled = 1;
#endif
#ifdef BRCM_ENET_SUPPORTED
brcm_enet_enabled = 1;
#endif
#ifdef BRCM_EMAC_1_SUPPORTED
brcm_emac_1_enabled = 1;
#endif
#ifdef BRCM_PCI_SUPPORTED
brcm_pci_enabled = 1;
#endif
#ifdef CONFIG_SMP
brcm_smp_enabled = 1;
#endif
#ifdef CONFIG_MIPS_BCM7118
/* detect 7118RNG board */
if( BDEV_RD(BCHP_CLKGEN_REG_START) == 0x1c )
brcm_sata_enabled = 0;
/* onchip DOCSIS owns the ENET */
brcm_enet_enabled = 0;
#endif
#ifdef CONFIG_MIPS_BCM7405
/* detect 7406 */
if(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) &
BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_sata_disable_MASK)
brcm_sata_enabled = 0;
switch(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) & 0xf) {
case 0x0:
/* 7405/7406 */
break;
case 0x1:
/* 7466 */
brcm_pci_enabled = 0;
brcm_emac_1_enabled = 0;
break;
case 0x3:
/* 7106 */
brcm_emac_1_enabled = 0;
brcm_smp_enabled = 0;
break;
case 0x4:
/* 7205 */
brcm_emac_1_enabled = 0;
break;
}
#endif
#if defined( CONFIG_MIPS_BCM7118 ) || defined( CONFIG_MIPS_BCM7401C0 ) \
|| defined( CONFIG_MIPS_BCM7402C0 ) || defined( CONFIG_MIPS_BCM3563 ) \
|| defined (CONFIG_MIPS_BCM3563C0)
/*need set bus to async mode before enabling the following*/
if(!(read_c0_diag4() & 0x400000))
{
int val=read_c0_diag4();
write_c0_diag4(val | 0x400000);
sprintf(msg, "CP0 reg 22 sel 0 to 5: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", read_c0_diag(), read_c0_diag1(), read_c0_diag2(), read_c0_diag3(), read_c0_diag4(), read_c0_diag5());
uart_puts(msg);
write_c0_config(0x80008083);
sprintf(msg, "CP0 reg 16 sel 0 to 1: 0x%08x 0x%08x \n", read_c0_config(), read_c0_config1());
uart_puts(msg);
}
/* Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT) */
BDEV_WR(0x0000040c, 0x264);
/* Enable Split Mode (BCHP_MISB_BRIDGE_MISB_SPLIT_MODE) */
BDEV_WR(0x00000410, 0x1);
#elif defined( CONFIG_MIPS_BCM7440A0 )
if(!(read_c0_diag4() & 0x400000))
{
int val=read_c0_diag4();
write_c0_diag4(val | 0x400000);
sprintf(msg, "CP0 reg 22 sel 0 to 5: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", read_c0_diag(), read_c0_diag1(), read_c0_diag2(), read_c0_diag3(), read_c0_diag4(), read_c0_diag5());
uart_puts(msg);
write_c0_config(0x80008083);
sprintf(msg, "CP0 reg 16 sel 0 to 1: 0x%08x 0x%08x \n", read_c0_config(), read_c0_config1());
uart_puts(msg);
}
/* Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT) */
BDEV_WR(0x0000040c, 0x2803);
#endif
#ifdef CONFIG_TIVO_MOJAVE
if ( cfe_seal != CFE_SEAL ){
goto noncfe;
}
#endif
/* Kernel arguments */
#ifdef CONFIG_MIPS_BRCM97XXX
/* For the 97xxx series STB, process CFE boot parms */
{
int i;
for (i=0; i<MAX_HWADDR; i++) {
gHwAddrs[i] = &privHwAddrs[i][0];
}
}
#ifdef CONFIG_TIVO_KONTIKI
res = get_cfe_boot_parms();
hasCfeParms = (res == 0);
#if 1 /* ###JLF */
if (gNumHwAddrs > 0)
{
printk("%s(): Got CFE MAC address "
"%02x:%02x:%02x:%02x:%02x:%02x\n",
__FUNCTION__,
gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2],
gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5]);
}
#endif
#ifdef BRCM_MEMORY_STRAPS
get_RAM_size();
#else
if(brcm_dram0_size == 0)
brcm_dram0_size = probe_memsize();
#ifndef CONFIG_DISCONTIGMEM
if(brcm_dram0_size > (256 << 20)) {
printk("Extra RAM beyond 256MB ignored. Please "
"use a kernel that supports DISCONTIG.\n");
brcm_dram0_size = 256 << 20;
}
#endif /* CONFIG_DISCONTIGMEM */
#endif /* BRCM_MEMORY_STRAPS */
// Make sure cfeBootParms is not empty or contains all white space
if (hasCfeParms) {
int i;
hasCfeParms = 0;
for (i=0; i < strlen(cfeBootParms); i++) {
if (isspace(cfeBootParms[i])) {
continue;
}
else if (cfeBootParms[i] == '\0') {
break; // and leave hasCfeParms false
}
else {
hasCfeParms = 1;
break;
}
}
}
#else /* if !defined(CONFIG_TIVO_KONTIKI) */
res = get_cfe_boot_parms(cfeBootParms, &gNumHwAddrs, gHwAddrs);
if(gNumHwAddrs <= 0) {
#if !defined(CONFIG_BRCM_PCI_SLAVE)
unsigned int i, mac = FLASH_MACADDR_ADDR, ok = 0;
for(i = 0; i < 3; i++) {
u16 word = readw((void *)mac);
if(word != 0x0000 && word != 0xffff)
ok = 1;
gHwAddrs[0][(i << 1)] = word & 0xff;
gHwAddrs[0][(i << 1) + 1] = word >> 8;
mac += 2;
}
/* display warning for all 00's, all ff's, or multicast */
if(! ok || (gHwAddrs[0][1] & 1)) {
printk(KERN_WARNING
"WARNING: read invalid MAC address "
"%02x:%02x:%02x:%02x:%02x:%02x from flash @ 0x%08x\n",
gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2],
gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5],
FLASH_MACADDR_ADDR);
}
#else
/* PCI slave mode - no EBI/flash available */
u8 fixed_macaddr[] = { 0x00, 0xc0, 0xa8, 0x74, 0x3b, 0x51 };
memcpy(&gHwAddrs[0][0], fixed_macaddr, sizeof(fixed_macaddr));
#endif
gNumHwAddrs = 1;
}
void __init prom_init(void)
{
#ifdef CONFIG_MIPS_BRCM97XXX
int hasCfeParms = 0;
int res = -1;
extern void determineBootFromFlashOrRom(void);
#endif
uart_init(27000000);
/* jipeng - mask out UPG L2 interrupt here */
BDEV_WR(BCHP_IRQ0_IRQEN, 0);
board_pinmux_setup();
/* Fill in platform information */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BRCM_STB;
#ifdef BRCM_SATA_SUPPORTED
brcm_sata_enabled = 1;
#endif
#ifdef BRCM_ENET_SUPPORTED
brcm_enet_enabled = 1;
#endif
#ifdef BRCM_EMAC_1_SUPPORTED
brcm_emac_1_enabled = 1;
#endif
#ifdef BRCM_PCI_SUPPORTED
brcm_pci_enabled = 1;
#endif
#ifdef CONFIG_SMP
brcm_smp_enabled = 1;
#endif
#ifdef CONFIG_MIPS_BCM7118
/* detect 7118RNG board */
if( BDEV_RD(BCHP_CLKGEN_REG_START) == 0x1c )
brcm_sata_enabled = 0;
/* onchip DOCSIS owns the ENET */
brcm_enet_enabled = 0;
#endif
#ifdef CONFIG_MIPS_BCM7405
/* detect 7406 */
if(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) &
BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_sata_disable_MASK)
brcm_sata_enabled = 0;
switch(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) & 0xf) {
case 0x0:
/* 7405/7406 */
break;
case 0x1:
/* 7466 */
brcm_pci_enabled = 0;
brcm_emac_1_enabled = 0;
break;
case 0x3:
/* 7106 */
brcm_emac_1_enabled = 0;
brcm_smp_enabled = 0;
break;
case 0x4:
case 0x6:
/* 7205/7213 */
brcm_emac_1_enabled = 0;
break;
}
#endif
#if defined(CONFIG_BMIPS3300)
// Set BIU to async mode
set_c0_brcm_bus_pll(1 << 22);
// Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT)
BDEV_WR(0x0000040c, 0x264);
// Enable Split Mode (BCHP_MISB_BRIDGE_MISB_SPLIT_MODE)
BDEV_WR(0x00000410, 0x1);
#endif
/* Kernel arguments */
#ifdef CONFIG_MIPS_BRCM97XXX
/* For the 97xxx series STB, process CFE boot parms */
{
int i;
for (i=0; i<MAX_HWADDR; i++) {
gHwAddrs[i] = &privHwAddrs[i][0];
}
}
res = get_cfe_boot_parms();
hasCfeParms = (res == 0);
#ifdef BRCM_MEMORY_STRAPS
get_RAM_size();
#else
if(brcm_dram0_size == 0)
brcm_dram0_size = probe_memsize();
#ifndef CONFIG_DISCONTIGMEM
if(brcm_dram0_size > (256 << 20)) {
printk("Extra RAM beyond 256MB ignored. Please "
"use a kernel that supports DISCONTIG.\n");
brcm_dram0_size = 256 << 20;
}
#endif /* CONFIG_DISCONTIGMEM */
#endif /* BRCM_MEMORY_STRAPS */
if(gNumHwAddrs <= 0) {
#if !defined(CONFIG_BRCM_PCI_SLAVE)
unsigned int i, mac = FLASH_MACADDR_ADDR, ok = 0;
for(i = 0; i < 3; i++) {
u16 word = readw((void *)mac);
if(word != 0x0000 && word != 0xffff)
ok = 1;
gHwAddrs[0][(i << 1)] = word & 0xff;
gHwAddrs[0][(i << 1) + 1] = word >> 8;
mac += 2;
}
/* display warning for all 00's, all ff's, or multicast */
if(! ok || (gHwAddrs[0][0] & 1)) {
u8 fixed_macaddr[] = { 0x00,0x00,0xde,0xad,0xbe,0xef };
printk(KERN_WARNING
"WARNING: read invalid MAC address "
"%02x:%02x:%02x:%02x:%02x:%02x from flash @ 0x%08x\n",
gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2],
gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5],
FLASH_MACADDR_ADDR);
memcpy(&gHwAddrs[0][0], fixed_macaddr,
sizeof(fixed_macaddr));
}
#else
/* PCI slave mode - no EBI/flash available */
u8 fixed_macaddr[] = { 0x00, 0xc0, 0xa8, 0x74, 0x3b, 0x51 };
memcpy(&gHwAddrs[0][0], fixed_macaddr, sizeof(fixed_macaddr));
#endif
gNumHwAddrs = 1;
}
