static void brcmf_sdio_ai_resetcore(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci, u16 coreid) { u8 idx; u32 regdata; idx = brcmf_sdio_chip_getinfidx(ci, coreid); /* must disable first to work for arbitrary current core state */ brcmf_sdio_ai_coredisable(sdiodev, ci, coreid); /* now do initialization sequence */ brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, BCMA_IOCTL_FGC | BCMA_IOCTL_CLK, NULL); regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, NULL); brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL, 0, NULL); udelay(1); brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, BCMA_IOCTL_CLK, NULL); regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL, NULL); udelay(1); }
static void brcmf_sdio_ai_resetcore(struct brcmf_sdio_dev *sdiodev, struct brcmf_chip *ci, u16 coreid, u32 pre_resetbits, u32 in_resetbits, u32 post_resetbits) { u8 idx; u32 regdata; u32 wrapbase; idx = brcmf_sdio_chip_getinfidx(ci, coreid); if (idx == BRCMF_MAX_CORENUM) return; wrapbase = ci->c_inf[idx].wrapbase; /* must disable first to work for arbitrary current core state */ brcmf_sdio_ai_coredisable(sdiodev, ci, coreid, pre_resetbits, in_resetbits); while (brcmf_sdiod_regrl(sdiodev, wrapbase + BCMA_RESET_CTL, NULL) & BCMA_RESET_CTL_RESET) { brcmf_sdiod_regwl(sdiodev, wrapbase + BCMA_RESET_CTL, 0, NULL); usleep_range(40, 60); } brcmf_sdiod_regwl(sdiodev, wrapbase + BCMA_IOCTL, post_resetbits | BCMA_IOCTL_CLK, NULL); regdata = brcmf_sdiod_regrl(sdiodev, wrapbase + BCMA_IOCTL, NULL); }