static void
intel_miptree_set_total_width_height(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
if (brw->gen == 4) {
/* Gen4 stores cube maps as 3D textures. */
assert(mt->physical_depth0 == 6);
brw_miptree_layout_texture_3d(brw, mt);
} else {
/* All other hardware stores cube maps as 2D arrays. */
brw_miptree_layout_texture_array(brw, mt);
}
break;
case GL_TEXTURE_3D:
if (brw->gen >= 9)
brw_miptree_layout_texture_array(brw, mt);
else
brw_miptree_layout_texture_3d(brw, mt);
break;
case GL_TEXTURE_1D_ARRAY:
case GL_TEXTURE_2D_ARRAY:
case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
case GL_TEXTURE_CUBE_MAP_ARRAY:
brw_miptree_layout_texture_array(brw, mt);
break;
default:
switch (mt->msaa_layout) {
case INTEL_MSAA_LAYOUT_UMS:
case INTEL_MSAA_LAYOUT_CMS:
brw_miptree_layout_texture_array(brw, mt);
break;
case INTEL_MSAA_LAYOUT_NONE:
case INTEL_MSAA_LAYOUT_IMS:
if (gen9_use_linear_1d_layout(brw, mt))
gen9_miptree_layout_1d(mt);
else
brw_miptree_layout_2d(mt);
break;
}
break;
}
DBG("%s: %dx%dx%d\n", __func__,
mt->total_width, mt->total_height, mt->cpp);
}
void
brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
{
bool multisampled = mt->num_samples > 1;
mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt->format);
mt->align_h =
intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
if (brw->gen == 4) {
/* Gen4 stores cube maps as 3D textures. */
assert(mt->physical_depth0 == 6);
brw_miptree_layout_texture_3d(brw, mt);
} else {
/* All other hardware stores cube maps as 2D arrays. */
brw_miptree_layout_texture_array(brw, mt);
}
break;
case GL_TEXTURE_3D:
brw_miptree_layout_texture_3d(brw, mt);
break;
case GL_TEXTURE_1D_ARRAY:
case GL_TEXTURE_2D_ARRAY:
case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
case GL_TEXTURE_CUBE_MAP_ARRAY:
brw_miptree_layout_texture_array(brw, mt);
break;
default:
switch (mt->msaa_layout) {
case INTEL_MSAA_LAYOUT_UMS:
case INTEL_MSAA_LAYOUT_CMS:
brw_miptree_layout_texture_array(brw, mt);
break;
case INTEL_MSAA_LAYOUT_NONE:
case INTEL_MSAA_LAYOUT_IMS:
brw_miptree_layout_2d(mt);
break;
}
break;
}
DBG("%s: %dx%dx%d\n", __FUNCTION__,
mt->total_width, mt->total_height, mt->cpp);
}
void
brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
{
bool multisampled = mt->num_samples > 1;
bool gen6_hiz_or_stencil = false;
if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
const GLenum base_format = _mesa_get_format_base_format(mt->format);
gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
}
if (gen6_hiz_or_stencil) {
/* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
* hardware doesn't support multiple mip levels on stencil/hiz.
*
* PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
* "The hierarchical depth buffer does not support the LOD field"
*
* PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
* "The stencil depth buffer does not support the LOD field"
*/
if (mt->format == MESA_FORMAT_S_UINT8) {
/* Stencil uses W tiling, so we force W tiling alignment for the
* ALL_SLICES_AT_EACH_LOD miptree layout.
*/
mt->align_w = 64;
mt->align_h = 64;
} else {
/* Depth uses Y tiling, so we force need Y tiling alignment for the
* ALL_SLICES_AT_EACH_LOD miptree layout.
*/
mt->align_w = 128 / mt->cpp;
mt->align_h = 32;
}
} else {
mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
mt->align_h =
intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
}
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
if (brw->gen == 4) {
/* Gen4 stores cube maps as 3D textures. */
assert(mt->physical_depth0 == 6);
brw_miptree_layout_texture_3d(brw, mt);
} else {
/* All other hardware stores cube maps as 2D arrays. */
brw_miptree_layout_texture_array(brw, mt);
}
break;
case GL_TEXTURE_3D:
if (brw->gen >= 9)
brw_miptree_layout_texture_array(brw, mt);
else
brw_miptree_layout_texture_3d(brw, mt);
break;
case GL_TEXTURE_1D_ARRAY:
case GL_TEXTURE_2D_ARRAY:
case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
case GL_TEXTURE_CUBE_MAP_ARRAY:
brw_miptree_layout_texture_array(brw, mt);
break;
default:
switch (mt->msaa_layout) {
case INTEL_MSAA_LAYOUT_UMS:
case INTEL_MSAA_LAYOUT_CMS:
brw_miptree_layout_texture_array(brw, mt);
break;
case INTEL_MSAA_LAYOUT_NONE:
case INTEL_MSAA_LAYOUT_IMS:
if (use_linear_1d_layout(brw, mt))
gen9_miptree_layout_1d(mt);
else
brw_miptree_layout_2d(mt);
break;
}
break;
}
DBG("%s: %dx%dx%d\n", __FUNCTION__,
mt->total_width, mt->total_height, mt->cpp);
}
void
brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
{
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
brw_miptree_layout_texture_array(intel, mt);
break;
case GL_TEXTURE_CUBE_MAP:
if (intel->gen >= 5) {
/* On Ironlake, cube maps are finally represented as just a series of
* MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated by a
* pitch of qpitch rows, where qpitch is defined by the equation given
* in Volume 1 of the BSpec.
*/
brw_miptree_layout_texture_array(intel, mt);
break;
}
assert(mt->physical_depth0 == 6);
/* FALLTHROUGH */
case GL_TEXTURE_3D: {
GLuint width = mt->physical_width0;
GLuint height = mt->physical_height0;
GLuint depth = mt->physical_depth0;
GLuint pack_x_pitch, pack_x_nr;
GLuint pack_y_pitch;
GLuint level;
mt->total_height = 0;
if (mt->compressed) {
mt->total_width = ALIGN(width, mt->align_w);
pack_y_pitch = (height + 3) / 4;
} else {
mt->total_width = mt->physical_width0;
pack_y_pitch = ALIGN(mt->physical_height0, mt->align_h);
}
pack_x_pitch = width;
pack_x_nr = 1;
for (level = mt->first_level ; level <= mt->last_level ; level++) {
GLint x = 0;
GLint y = 0;
GLint q, j;
intel_miptree_set_level_info(mt, level,
0, mt->total_height,
width, height, depth);
for (q = 0; q < depth; /* empty */) {
for (j = 0; j < pack_x_nr && q < depth; j++, q++) {
intel_miptree_set_image_offset(mt, level, q, x, y);
x += pack_x_pitch;
}
if (x > mt->total_width)
mt->total_width = x;
x = 0;
y += pack_y_pitch;
}
mt->total_height += y;
width = minify(width);
height = minify(height);
if (mt->target == GL_TEXTURE_3D)
depth = minify(depth);
if (mt->compressed) {
pack_y_pitch = (height + 3) / 4;
if (pack_x_pitch > ALIGN(width, mt->align_w)) {
pack_x_pitch = ALIGN(width, mt->align_w);
pack_x_nr <<= 1;
}
} else {
pack_x_nr <<= 1;
if (pack_x_pitch > 4) {
pack_x_pitch >>= 1;
}
if (pack_y_pitch > 2) {
pack_y_pitch >>= 1;
pack_y_pitch = ALIGN(pack_y_pitch, mt->align_h);
}
}
}
/* The 965's sampler lays cachelines out according to how accesses
* in the texture surfaces run, so they may be "vertical" through
* memory. As a result, the docs say in Surface Padding Requirements:
* Sampling Engine Surfaces that two extra rows of padding are required.
*/
if (mt->target == GL_TEXTURE_CUBE_MAP)
mt->total_height += 2;
break;
}
