int puc_cardbus_match(struct device *parent, void *match, void *aux) { struct cardbus_attach_args *ca = aux; struct cardbus_devfunc *ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; cardbusreg_t bhlc, reg; bhlc = cardbus_conf_read(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG); if (PCI_HDRTYPE_TYPE(bhlc) != 0) return(0); /* this one is some sort of a bridge and not a puc */ if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_OXFORD2 && PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_OXFORD2_EXSYS_EX41098) return (0); reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_SUBSYS_ID_REG); if (puc_find_description(PCI_VENDOR(ca->ca_id), PCI_PRODUCT(ca->ca_id), PCI_VENDOR(reg), PCI_PRODUCT(reg))) return (10); return (0); }
void com_cardbus_setup(struct com_cardbus_softc *csc) { cardbus_devfunc_t ct = csc->cc_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; cardbusreg_t reg; cardbus_conf_write(cc, cf, csc->cc_tag, csc->cc_reg, csc->cc_base); /* enable accesses on cardbus bridge */ cf->cardbus_ctrl(cc, csc->cc_cben); cf->cardbus_ctrl(cc, CARDBUS_BM_ENABLE); /* and the card itself */ reg = cardbus_conf_read(cc, cf, csc->cc_tag, CARDBUS_COMMAND_STATUS_REG); reg &= ~(CARDBUS_COMMAND_IO_ENABLE | CARDBUS_COMMAND_MEM_ENABLE); reg |= csc->cc_csr; cardbus_conf_write(cc, cf, csc->cc_tag, CARDBUS_COMMAND_STATUS_REG, reg); /* * Make sure the latency timer is set to some reasonable * value. */ reg = cardbus_conf_read(cc, cf, csc->cc_tag, CARDBUS_BHLC_REG); if (CARDBUS_LATTIMER(reg) < 0x20) { reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT); reg |= (0x20 << CARDBUS_LATTIMER_SHIFT); cardbus_conf_write(cc, cf, csc->cc_tag, CARDBUS_BHLC_REG, reg); } }
void rtw_cardbus_setup(struct rtw_cardbus_softc *csc) { struct rtw_softc *sc = &csc->sc_rtw; cardbus_devfunc_t ct = csc->sc_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; pcireg_t reg; int pmreg; if (cardbus_get_capability(cc, cf, csc->sc_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { reg = cardbus_conf_read(cc, cf, csc->sc_tag, pmreg + 4) & 0x03; #if 1 /* XXX Probably not right for CardBus. */ if (reg == 3) { /* * The card has lost all configuration data in * this state, so punt. */ printf("%s: unable to wake up from power state D3\n", sc->sc_dev.dv_xname); return; } #endif if (reg != 0) { printf("%s: waking up from power state D%d\n", sc->sc_dev.dv_xname, reg); cardbus_conf_write(cc, cf, csc->sc_tag, pmreg + 4, 0); } } /* Program the BAR. */ cardbus_conf_write(cc, cf, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val); /* Make sure the right access type is on the CardBus bridge. */ (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben); (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the appropriate bits in the PCI CSR. */ reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG); reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE); reg |= csc->sc_csr; cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG, reg); /* * Make sure the latency timer is set to some reasonable * value. */ reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG); if (CARDBUS_LATTIMER(reg) < 0x20) { reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT); reg |= (0x20 << CARDBUS_LATTIMER_SHIFT); cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg); } }
void ex_cardbus_setup(struct ex_cardbus_softc *csc) { cardbus_devfunc_t ct = csc->sc_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; cardbusreg_t reg; (void)cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0); /* Program the BAR */ cardbus_conf_write(cc, cf, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val); /* Make sure the right access type is on the CardBus bridge. */ (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE); if (csc->sc_cardtype == EX_CB_CYCLONE) { /* Program the BAR */ cardbus_conf_write(cc, cf, csc->sc_tag, csc->sc_bar_reg1, csc->sc_bar_val1); /* * Make sure CardBus brigde can access memory space. Usually * memory access is enabled by BIOS, but some BIOSes do not * enable it. */ (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE); } (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the appropriate bits in the CARDBUS CSR. */ reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG); reg |= csc->sc_csr; cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG, reg); /* * set latency timer */ reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG); if (CARDBUS_LATTIMER(reg) < 0x20) { /* at least the value of latency timer should 0x20. */ DPRINTF(("if_ex_cardbus: lattimer 0x%x -> 0x20\n", CARDBUS_LATTIMER(reg))); reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT); reg |= (0x20 << CARDBUS_LATTIMER_SHIFT); cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg); } }
void malo_cardbus_setup(struct malo_cardbus_softc *csc) { cardbus_devfunc_t ct = csc->sc_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; pcireg_t reg; /* program the BAR */ cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BASE0_REG, csc->sc_bar1_val); cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BASE1_REG, csc->sc_bar2_val); /* make sure the right access type is on the cardbus bridge */ (*cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE); (*cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* enable the appropriate bits in the PCI CSR */ reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG); reg |= CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_MEM_ENABLE; cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG, reg); }
void atw_cardbus_setup(struct atw_cardbus_softc *csc) { #ifdef notyet struct atw_softc *sc = &csc->sc_atw; #endif cardbus_devfunc_t ct = csc->sc_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; pcireg_t reg; #ifdef notyet (void)cardbus_setpowerstate(sc->sc_dev.dv_xname, ct, csc->sc_tag, PCI_PWR_D0); #endif /* Program the BAR. */ cardbus_conf_write(cc, cf, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val); /* Make sure the right access type is on the CardBus bridge. */ (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben); (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the appropriate bits in the PCI CSR. */ reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG); reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE); reg |= csc->sc_csr; cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG, reg); /* * Make sure the latency timer is set to some reasonable * value. */ reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG); if (CARDBUS_LATTIMER(reg) < 0x20) { reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT); reg |= (0x20 << CARDBUS_LATTIMER_SHIFT); cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg); } }
void ath_cardbus_setup(struct ath_cardbus_softc *csc) { cardbus_devfunc_t ct = csc->sc_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; int rc; pcireg_t reg; if ((rc = cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0)) != 0) aprint_debug("%s: cardbus_set_powerstate %d\n", __func__, rc); /* Program the BAR. */ cardbus_conf_write(cc, cf, csc->sc_tag, ATH_PCI_MMBA, csc->sc_bar_val); /* Enable the appropriate bits in the PCI CSR. */ reg = cardbus_conf_read(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG); reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; cardbus_conf_write(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg); }
void re_cardbus_setup(struct re_cardbus_softc *csc) { struct rtk_softc *sc = &csc->sc_rtk; cardbus_devfunc_t ct = csc->sc_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; pcireg_t reg, command; int pmreg; /* * Handle power management nonsense. */ if (cardbus_get_capability(cc, cf, csc->sc_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { command = cardbus_conf_read(cc, cf, csc->sc_tag, pmreg + PCI_PMCSR); if (command & PCI_PMCSR_STATE_MASK) { pcireg_t iobase, membase, irq; /* Save important PCI config data. */ iobase = cardbus_conf_read(cc, cf, csc->sc_tag, RTK_PCI_LOIO); membase = cardbus_conf_read(cc, cf,csc->sc_tag, RTK_PCI_LOMEM); irq = cardbus_conf_read(cc, cf,csc->sc_tag, CARDBUS_INTERRUPT_REG); /* Reset the power state. */ aprint_normal_dev(sc->sc_dev, "chip is in D%d power mode -- setting to D0\n", command & PCI_PMCSR_STATE_MASK); command &= ~PCI_PMCSR_STATE_MASK; cardbus_conf_write(cc, cf, csc->sc_tag, pmreg + PCI_PMCSR, command); /* Restore PCI config data. */ cardbus_conf_write(cc, cf, csc->sc_tag, RTK_PCI_LOIO, iobase); cardbus_conf_write(cc, cf, csc->sc_tag, RTK_PCI_LOMEM, membase); cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_INTERRUPT_REG, irq); } } /* Program the BAR */ cardbus_conf_write(cc, cf, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val); /* Make sure the right access type is on the CardBus bridge. */ (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben); (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the appropriate bits in the CARDBUS CSR. */ reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG); reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE); reg |= csc->sc_csr; cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG, reg); /* * Make sure the latency timer is set to some reasonable * value. */ reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG); if (CARDBUS_LATTIMER(reg) < 0x40) { reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT); reg |= (0x40 << CARDBUS_LATTIMER_SHIFT); cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg); } }
/* * static int cardbus_io_find(cardbus_chipset_tag_t cc, * cardbus_function_tag_t cf, pcitag_t tag, * int reg, pcireg_t type, bus_addr_t *basep, * bus_size_t *sizep, int *flagsp) * This code is stolen from sys/dev/pci_map.c. */ static int cardbus_io_find( cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, pcitag_t tag, int reg, pcireg_t type, bus_addr_t *basep, bus_size_t *sizep, int *flagsp) { pcireg_t address, mask; int s; /* EXT ROM is able to map on memory space ONLY. */ if (reg == CARDBUS_ROM_REG) { return 1; } if(reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) { panic("cardbus_io_find: bad request"); } /* * Section 6.2.5.1, `Address Maps', tells us that: * * 1) The builtin software should have already mapped the device in a * reasonable way. * * 2) A device which wants 2^n bytes of memory will hardwire the bottom * n bits of the address to 0. As recommended, we write all 1s and see * what we get back. */ s = splhigh(); address = cardbus_conf_read(cc, cf, tag, reg); cardbus_conf_write(cc, cf, tag, reg, 0xffffffff); mask = cardbus_conf_read(cc, cf, tag, reg); cardbus_conf_write(cc, cf, tag, reg, address); splx(s); if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) { printf("cardbus_io_find: expected type i/o, found mem\n"); return 1; } if (PCI_MAPREG_IO_SIZE(mask) == 0) { printf("cardbus_io_find: void region\n"); return 1; } if (basep != 0) { *basep = PCI_MAPREG_IO_ADDR(address); } if (sizep != 0) { *sizep = PCI_MAPREG_IO_SIZE(mask); } if (flagsp != 0) { *flagsp = 0; } return 0; }
/* * static int cardbus_mem_find(cardbus_chipset_tag_t cc, * cardbus_function_tag_t cf, pcitag_t tag, * int reg, pcireg_t type, bus_addr_t *basep, * bus_size_t *sizep, int *flagsp) * This code is stolen from sys/dev/pci_map.c. */ static int cardbus_mem_find(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, pcitag_t tag, int reg, pcireg_t type, bus_addr_t *basep, bus_size_t *sizep, int *flagsp) { pcireg_t address, mask; int s; if (reg != CARDBUS_ROM_REG && (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3))) { panic("cardbus_mem_find: bad request"); } /* * Section 6.2.5.1, `Address Maps', tells us that: * * 1) The builtin software should have already mapped the device in a * reasonable way. * * 2) A device which wants 2^n bytes of memory will hardwire the bottom * n bits of the address to 0. As recommended, we write all 1s and see * what we get back. */ s = splhigh(); address = cardbus_conf_read(cc, cf, tag, reg); cardbus_conf_write(cc, cf, tag, reg, 0xffffffff); mask = cardbus_conf_read(cc, cf, tag, reg); cardbus_conf_write(cc, cf, tag, reg, address); splx(s); if (reg != CARDBUS_ROM_REG) { /* memory space BAR */ if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_MEM) { printf("cardbus_mem_find: expected type mem, found i/o\n"); return 1; } if (PCI_MAPREG_MEM_TYPE(address) != PCI_MAPREG_MEM_TYPE(type)) { printf("cardbus_mem_find: expected mem type %08x, found %08x\n", PCI_MAPREG_MEM_TYPE(type), PCI_MAPREG_MEM_TYPE(address)); return 1; } } if (PCI_MAPREG_MEM_SIZE(mask) == 0) { printf("cardbus_mem_find: void region\n"); return 1; } switch (PCI_MAPREG_MEM_TYPE(address)) { case PCI_MAPREG_MEM_TYPE_32BIT: case PCI_MAPREG_MEM_TYPE_32BIT_1M: break; case PCI_MAPREG_MEM_TYPE_64BIT: printf("cardbus_mem_find: 64-bit memory mapping register\n"); return 1; default: printf("cardbus_mem_find: reserved mapping register type\n"); return 1; } if (basep != 0) { *basep = PCI_MAPREG_MEM_ADDR(address); } if (sizep != 0) { *sizep = PCI_MAPREG_MEM_SIZE(mask); } if (flagsp != 0) { *flagsp = PCI_MAPREG_MEM_PREFETCHABLE(address) ? BUS_SPACE_MAP_PREFETCHABLE : 0; } return 0; }
void uhci_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct uhci_cardbus_softc *sc = (struct uhci_cardbus_softc *)self; struct cardbus_attach_args *ca = aux; cardbus_devfunc_t ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; cardbusreg_t csr; char devinfo[256]; usbd_status r; const char *vendor; const char *devname = sc->sc.sc_bus.bdev.dv_xname; cardbus_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo)); printf(" %s", devinfo); /* Map I/O registers */ if (Cardbus_mapreg_map(ct, PCI_CBIO, CARDBUS_MAPREG_TYPE_IO, 0, &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { printf("%s: can't map io space\n", devname); return; } /* Disable interrupts, so we don't get any spurious ones. */ bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); sc->sc_cc = cc; sc->sc_cf = cf; sc->sc_ct = ct; sc->sc.sc_bus.dmatag = ca->ca_dmat; (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE); (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the device. */ csr = cardbus_conf_read(cc, cf, ca->ca_tag, CARDBUS_COMMAND_STATUS_REG); cardbus_conf_write(cc, cf, ca->ca_tag, CARDBUS_COMMAND_STATUS_REG, csr | CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_IO_ENABLE); sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_USB, uhci_intr, sc, devname); if (sc->sc_ih == NULL) { printf("%s: couldn't establish interrupt\n", devname); return; } printf(": irq %d\n", ca->ca_intrline); /* Set LEGSUP register to its default value. */ cardbus_conf_write(cc, cf, ca->ca_tag, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN); switch(cardbus_conf_read(cc, cf, ca->ca_tag, PCI_USBREV) & PCI_USBREV_MASK) { case PCI_USBREV_PRE_1_0: sc->sc.sc_bus.usbrev = USBREV_PRE_1_0; break; case PCI_USBREV_1_0: sc->sc.sc_bus.usbrev = USBREV_1_0; break; case PCI_USBREV_1_1: sc->sc.sc_bus.usbrev = USBREV_1_1; break; default: sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; break; } uhci_run(&sc->sc, 0); /* stop the controller */ /* disable interrupts */ bus_space_barrier(sc->sc.iot, sc->sc.ioh, 0, sc->sc.sc_size, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); /* Figure out vendor for root hub descriptor. */ vendor = cardbus_findvendor(ca->ca_id); sc->sc.sc_id_vendor = CARDBUS_VENDOR(ca->ca_id); if (vendor) strlcpy(sc->sc.sc_vendor, vendor, sizeof (sc->sc.sc_vendor)); else snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), "vendor 0x%04x", CARDBUS_VENDOR(ca->ca_id)); r = uhci_init(&sc->sc); if (r != USBD_NORMAL_COMPLETION) { printf("%s: init failed, error=%d\n", devname, r); bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); return; } /* Attach usb device. */ sc->sc.sc_child = config_found((void *)sc, &sc->sc.sc_bus, usbctlprint); }
void puc_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct puc_cardbus_softc *csc = (struct puc_cardbus_softc *)self; struct puc_softc *sc = &csc->sc_psc; struct cardbus_attach_args *ca = aux; struct cardbus_devfunc *ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; struct puc_attach_args paa; cardbusreg_t reg; int i; Cardbus_function_enable(ct); csc->ct = ct; reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_SUBSYS_ID_REG); sc->sc_desc = puc_find_description(PCI_VENDOR(ca->ca_id), PCI_PRODUCT(ca->ca_id), PCI_VENDOR(reg), PCI_PRODUCT(reg)); puc_print_ports(sc->sc_desc); /* the fifth one is some memory we dunno */ for (i = 0; i < PUC_NBARS; i++) { cardbusreg_t type; int bar; sc->sc_bar_mappings[i].mapped = 0; bar = PCI_MAPREG_START + 4 * i; if (!cardbus_mapreg_probe(cc, cf, ca->ca_tag, bar, &type)) continue; if (!(sc->sc_bar_mappings[i].mapped = !Cardbus_mapreg_map(ct, bar, type, 0, &sc->sc_bar_mappings[i].t, &sc->sc_bar_mappings[i].h, &sc->sc_bar_mappings[i].a, &sc->sc_bar_mappings[i].s))) printf("%s: couldn't map BAR at offset 0x%lx\n", sc->sc_dev.dv_xname, (long)bar); sc->sc_bar_mappings[i].type = type; } csc->intrline = ca->ca_intrline; if (cardbus_get_capability(cc, cf, ca->ca_tag, PCI_CAP_PWRMGMT, ®, 0)) { reg = cardbus_conf_read(cc, cf, ca->ca_tag, reg + 4) & 3; if (reg) { printf("%s: awakening from state D%d\n", sc->sc_dev.dv_xname, reg); cardbus_conf_write(cc, cf, ca->ca_tag, reg + 4, 0); } } (*cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE); (*cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE); (*cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); paa.puc = sc; paa.hwtype = COM_UART_OX16C950; /* XXX */ paa.intr_string = &puc_cardbus_intr_string; paa.intr_establish = &puc_cardbus_intr_establish; puc_common_attach(sc, &paa); }
void adv_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct cardbus_attach_args *ca = aux; struct adv_cardbus_softc *csc = device_private(self); struct asc_softc *sc = &csc->sc_adv; cardbus_devfunc_t ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; bus_space_tag_t iot; bus_space_handle_t ioh; pcireg_t reg; u_int8_t latency = 0x20; sc->sc_flags = 0; if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_ADVSYS) { switch (PCI_PRODUCT(ca->ca_id)) { case PCI_PRODUCT_ADVSYS_1200A: printf(": AdvanSys ASC1200A SCSI adapter\n"); latency = 0; break; case PCI_PRODUCT_ADVSYS_1200B: printf(": AdvanSys ASC1200B SCSI adapter\n"); latency = 0; break; case PCI_PRODUCT_ADVSYS_ULTRA: switch (PCI_REVISION(ca->ca_class)) { case ASC_PCI_REVISION_3050: printf(": AdvanSys ABP-9xxUA SCSI adapter\n"); break; case ASC_PCI_REVISION_3150: printf(": AdvanSys ABP-9xxU SCSI adapter\n"); break; } break; default: printf(": unknown model!\n"); return; } } csc->sc_ct = ct; csc->sc_tag = ca->ca_tag; csc->sc_intrline = ca->ca_intrline; csc->sc_cbenable = 0; /* * Map the device. */ csc->sc_csr = PCI_COMMAND_MASTER_ENABLE; #ifdef ADV_CARDBUS_ALLOW_MEMIO if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_MMBA, PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, &iot, &ioh, NULL, &csc->sc_size) == 0) { #ifdef ADV_CARDBUS_DEBUG printf("%s: memio enabled\n", DEVNAME(sc)); #endif csc->sc_cbenable = CARDBUS_MEM_ENABLE; csc->sc_csr |= PCI_COMMAND_MEM_ENABLE; } else #endif if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_IOBA, PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, &csc->sc_size) == 0) { #ifdef ADV_CARDBUS_DEBUG printf("%s: io enabled\n", DEVNAME(sc)); #endif csc->sc_cbenable = CARDBUS_IO_ENABLE; csc->sc_csr |= PCI_COMMAND_IO_ENABLE; } else { aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); return; } /* Make sure the right access type is on the CardBus bridge. */ (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cbenable); (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the appropriate bits in the PCI CSR. */ reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG); reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); reg |= csc->sc_csr; cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg); /* * Make sure the latency timer is set to some reasonable * value. */ reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_BHLC_REG); if (PCI_LATTIMER(reg) < latency) { reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); reg |= (latency << PCI_LATTIMER_SHIFT); cardbus_conf_write(cc, cf, ca->ca_tag, PCI_BHLC_REG, reg); } ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); ASC_SET_CHIP_STATUS(iot, ioh, 0); sc->sc_iot = iot; sc->sc_ioh = ioh; sc->sc_dmat = ca->ca_dmat; sc->pci_device_id = ca->ca_id; sc->bus_type = ASC_IS_PCI; sc->chip_version = ASC_GET_CHIP_VER_NO(iot, ioh); /* * Initialize the board */ if (adv_init(sc)) { printf("adv_init failed\n"); return; } /* * Establish the interrupt. */ sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO, adv_intr, sc); if (sc->sc_ih == NULL) { aprint_error_dev(&sc->sc_dev, "unable to establish interrupt\n"); return; } /* * Attach. */ adv_attach(sc); }
void atw_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct atw_cardbus_softc *csc = (void *)self; struct atw_softc *sc = &csc->sc_atw; struct cardbus_attach_args *ca = aux; cardbus_devfunc_t ct = ca->ca_ct; bus_addr_t adr; sc->sc_dmat = ca->ca_dmat; csc->sc_ct = ct; csc->sc_tag = ca->ca_tag; /* * Power management hooks. */ sc->sc_enable = atw_cardbus_enable; sc->sc_disable = atw_cardbus_disable; sc->sc_power = atw_cardbus_power; /* Get revision info. */ sc->sc_rev = PCI_REVISION(ca->ca_class); #if 0 printf(": signature %08x\n%s", cardbus_conf_read(ct->ct_cc, ct->ct_cf, csc->sc_tag, 0x80), sc->sc_dev.dv_xname); #endif /* * Map the device. */ csc->sc_csr = CARDBUS_COMMAND_MASTER_ENABLE; if (Cardbus_mapreg_map(ct, ATW_PCI_MMBA, CARDBUS_MAPREG_TYPE_MEM, 0, &sc->sc_st, &sc->sc_sh, &adr, &csc->sc_mapsize) == 0) { #if 0 printf(": atw_cardbus_attach mapped %d bytes mem space\n%s", csc->sc_mapsize, sc->sc_dev.dv_xname); #endif csc->sc_cben = CARDBUS_MEM_ENABLE; csc->sc_csr |= CARDBUS_COMMAND_MEM_ENABLE; csc->sc_bar_reg = ATW_PCI_MMBA; csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM; } else if (Cardbus_mapreg_map(ct, ATW_PCI_IOBA, CARDBUS_MAPREG_TYPE_IO, 0, &sc->sc_st, &sc->sc_sh, &adr, &csc->sc_mapsize) == 0) { #if 0 printf(": atw_cardbus_attach mapped %d bytes I/O space\n%s", csc->sc_mapsize, sc->sc_dev.dv_xname); #endif csc->sc_cben = CARDBUS_IO_ENABLE; csc->sc_csr |= CARDBUS_COMMAND_IO_ENABLE; csc->sc_bar_reg = ATW_PCI_IOBA; csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_IO; } else { printf(": unable to map device registers\n"); return; } /* * Bring the chip out of powersave mode and initialize the * configuration registers. */ atw_cardbus_setup(csc); /* Remember which interrupt line. */ csc->sc_intrline = ca->ca_intrline; printf(": revision %d.%d: irq %d\n", (sc->sc_rev >> 4) & 0xf, sc->sc_rev & 0xf, csc->sc_intrline); #if 0 /* * The CardBus cards will make it to store-and-forward mode as * soon as you put them under any kind of load, so just start * out there. */ sc->sc_txthresh = 3; /* TBD name constant */ #endif /* * Finish off the attach. */ atw_attach(sc); ATW_WRITE(sc, ATW_FER, ATW_FER_INTR); /* * Power down the socket. */ Cardbus_function_disable(csc->sc_ct); }
static void uhci_cardbus_attach(device_t parent, device_t self, void *aux) { struct uhci_cardbus_softc *sc = device_private(self); struct cardbus_attach_args *ca = (struct cardbus_attach_args *)aux; cardbus_devfunc_t ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; cardbustag_t tag = ca->ca_tag; cardbusreg_t csr; const char *vendor; const char *devname = device_xname(self); char devinfo[256]; usbd_status r; sc->sc.sc_dev = self; sc->sc.sc_bus.hci_private = sc; cardbus_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo)); printf(": %s (rev. 0x%02x)\n", devinfo, CARDBUS_REVISION(ca->ca_class)); /* Map I/O registers */ if (Cardbus_mapreg_map(ct, CARDBUS_CBIO, CARDBUS_MAPREG_TYPE_IO, 0, &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { printf("%s: can't map i/o space\n", devname); return; } sc->sc_cc = cc; sc->sc_cf = cf; sc->sc_ct = ct; sc->sc_tag = tag; sc->sc.sc_bus.dmatag = ca->ca_dmat; #if rbus #else XXX (ct->ct_cf->cardbus_io_open)(cc, 0, iob, iob + 0x40); #endif (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE); (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the device. */ csr = cardbus_conf_read(cc, cf, tag, CARDBUS_COMMAND_STATUS_REG); cardbus_conf_write(cc, cf, tag, CARDBUS_COMMAND_STATUS_REG, csr | CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_IO_ENABLE); /* Disable interrupts, so we don't get any spurious ones. */ bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); /* Map and establish the interrupt. */ sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_USB, uhci_intr, sc); if (sc->sc_ih == NULL) { printf("%s: couldn't establish interrupt\n", devname); return; } /* Set LEGSUP register to its default value. */ cardbus_conf_write(cc, cf, tag, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN); switch(cardbus_conf_read(cc, cf, tag, PCI_USBREV) & PCI_USBREV_MASK) { case PCI_USBREV_PRE_1_0: sc->sc.sc_bus.usbrev = USBREV_PRE_1_0; break; case PCI_USBREV_1_0: sc->sc.sc_bus.usbrev = USBREV_1_0; break; case PCI_USBREV_1_1: sc->sc.sc_bus.usbrev = USBREV_1_1; break; default: sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; break; } /* Figure out vendor for root hub descriptor. */ vendor = cardbus_findvendor(ca->ca_id); sc->sc.sc_id_vendor = CARDBUS_VENDOR(ca->ca_id); if (vendor) strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); else snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), "vendor 0x%04x", CARDBUS_VENDOR(ca->ca_id)); r = uhci_init(&sc->sc); if (r != USBD_NORMAL_COMPLETION) { printf("%s: init failed, error=%d\n", devname, r); /* Avoid spurious interrupts. */ cardbus_intr_disestablish(sc->sc_cc, sc->sc_cf, sc->sc_ih); sc->sc_ih = NULL; return; } #if NEHCI_CARDBUS > 0 usb_cardbus_add(&sc->sc_cardbus, ca, self); #endif /* Attach usb device. */ sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); }
static void njs_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct cardbus_attach_args *ca = aux; struct njsc32_cardbus_softc *csc = (void *) self; struct njsc32_softc *sc = &csc->sc_njsc32; const struct njsc32_cardbus_product *prod; cardbus_devfunc_t ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; pcireg_t reg; int csr; u_int8_t latency = 0x20; if ((prod = njs_cardbus_lookup(ca)) == NULL) panic("njs_cardbus_attach"); printf(": Workbit NinjaSCSI-32 SCSI adapter\n"); sc->sc_model = prod->p_model; sc->sc_clk = prod->p_clk; csc->sc_ct = ct; csc->sc_tag = ca->ca_tag; csc->sc_intrline = ca->ca_intrline; /* * Map the device. */ csr = PCI_COMMAND_MASTER_ENABLE; /* * Map registers. * Try memory map first, and then try I/O. */ if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM, PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_regt, &csc->sc_regmaph, NULL, &csc->sc_regmap_size) == 0) { if (bus_space_subregion(sc->sc_regt, csc->sc_regmaph, NJSC32_MEMOFFSET_REG, NJSC32_REGSIZE, &sc->sc_regh) != 0) { /* failed -- undo map and try I/O */ Cardbus_mapreg_unmap(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM, sc->sc_regt, csc->sc_regmaph, csc->sc_regmap_size); goto try_io; } #ifdef NJSC32_DEBUG printf("%s: memory space mapped\n", sc->sc_dev.dv_xname); #endif csr |= PCI_COMMAND_MEM_ENABLE; sc->sc_flags = NJSC32_MEM_MAPPED; (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE); } else { try_io: if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_IO, PCI_MAPREG_TYPE_IO, 0, &sc->sc_regt, &sc->sc_regh, NULL, &csc->sc_regmap_size) == 0) { #ifdef NJSC32_DEBUG printf("%s: io space mapped\n", sc->sc_dev.dv_xname); #endif csr |= PCI_COMMAND_IO_ENABLE; sc->sc_flags = NJSC32_IO_MAPPED; (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE); } else { printf("%s: unable to map device registers\n", sc->sc_dev.dv_xname); return; } } /* Make sure the right access type is on the CardBus bridge. */ (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the appropriate bits in the PCI CSR. */ reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG); reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); reg |= csr; cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg); /* * Make sure the latency timer is set to some reasonable * value. */ reg = cardbus_conf_read(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG); if (CARDBUS_LATTIMER(reg) < latency) { reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT); reg |= (latency << CARDBUS_LATTIMER_SHIFT); cardbus_conf_write(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG, reg); } sc->sc_dmat = ca->ca_dmat; /* * Establish the interrupt. */ sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO, njsc32_intr, sc); if (sc->sc_ih == NULL) { printf("%s: unable to establish interrupt at %d\n", sc->sc_dev.dv_xname, ca->ca_intrline); return; } printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname, ca->ca_intrline); /* CardBus device cannot supply termination power. */ sc->sc_flags |= NJSC32_CANNOT_SUPPLY_TERMPWR; /* attach */ njsc32_attach(sc); }