/*!
\brief open spi communication port to be used for communicating with a SimpleLink device
Given an interface name and option flags, this function opens the spi communication port
and creates a file descriptor. This file descriptor can be used afterwards to read and
write data from and to this specific spi channel.
The SPI speed, clock polarity, clock phase, chip select and all other attributes are all
set to hardcoded values in this function.
\param ifName - points to the interface name/path. The interface name is an
optional attributes that the simple link driver receives
on opening the device. in systems that the spi channel is
not implemented as part of the os device drivers, this
parameter could be NULL.
\param flags - option flags
\return upon successful completion, the function shall open the spi channel and return
a non-negative integer representing the file descriptor.
Otherwise, -1 shall be returned
\sa spi_Close , spi_Read , spi_Write
\note
\warning
*/
Fd_t spi_Open(char *ifName, unsigned long flags)
{
unsigned long ulBase;
//NWP master interface
ulBase = LSPI_BASE;
//Enable MCSPIA2
PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);
//Disable Chip Select
SPICSDisable(ulBase);
//Disable SPI Channel
SPIDisable(ulBase);
// Reset SPI
SPIReset(ulBase);
//
// Configure SPI interface
//
SPIConfigSetExpClk(ulBase,PRCMPeripheralClockGet(PRCM_LSPI),
SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_0,
(SPI_SW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH |
SPI_WL_32));
if(PRCMPeripheralStatusGet(PRCM_UDMA))
{
g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0;
}
else
{
g_ucDMAEnabled = 0;
}
#ifdef SL_CPU_MODE
g_ucDMAEnabled = 0;
#endif
if(g_ucDMAEnabled)
{
memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout));
//g_ucDout[0]=0xFF;
//Simplelink_UDMAInit();
// Set DMA channel
cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX);
cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX);
SPIFIFOEnable(ulBase,SPI_RX_FIFO);
SPIFIFOEnable(ulBase,SPI_TX_FIFO);
SPIDmaEnable(ulBase,SPI_RX_DMA);
SPIDmaEnable(ulBase,SPI_TX_DMA);
SPIFIFOLevelSet(ulBase,1,1);
#if defined(SL_PLATFORM_MULTI_THREADED)
osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1);
SPIIntEnable(ulBase,SPI_INT_EOW);
osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1);
#else
IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler);
IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1);
IntEnable(INT_LSPI);
SPIIntEnable(ulBase,SPI_INT_EOW);
g_cDummy = 0x0;
#endif
}
SPIEnable(ulBase);
g_SpiFd = 1;
return g_SpiFd;
}
Fd_t spi_Open(char *ifName, unsigned long flags)
{
unsigned long ulBase;
unsigned long ulSpiBitRate;
tROMVersion* pRomVersion = (tROMVersion *)(ROM_VERSION_ADDR);
//NWP master interface
ulBase = LSPI_BASE;
//Enable MCSPIA2
MAP_PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);
//Disable Chip Select
MAP_SPICSDisable(ulBase);
//Disable SPI Channel
MAP_SPIDisable(ulBase);
// Reset SPI
MAP_SPIReset(ulBase);
//
// Configure SPI interface
//
if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_21 )
{
ulSpiBitRate = SPI_RATE_13M;
}
else if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_32)
{
ulSpiBitRate = SPI_RATE_13M;
}
else if(pRomVersion->ucMinorVerNum >= ROM_VER_PG1_33)
{
ulSpiBitRate = SPI_RATE_20M;
}
MAP_SPIConfigSetExpClk(ulBase,MAP_PRCMPeripheralClockGet(PRCM_LSPI),
ulSpiBitRate,SPI_MODE_MASTER,SPI_SUB_MODE_0,
(SPI_SW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH |
SPI_WL_32));
if(MAP_PRCMPeripheralStatusGet(PRCM_UDMA))
{
g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0;
}
else
{
g_ucDMAEnabled = 0;
}
#ifdef SL_CPU_MODE
g_ucDMAEnabled = 0;
#endif
if(g_ucDMAEnabled)
{
memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout));
// Set DMA channel
cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX);
cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX);
MAP_SPIFIFOEnable(ulBase,SPI_RX_FIFO);
MAP_SPIFIFOEnable(ulBase,SPI_TX_FIFO);
MAP_SPIDmaEnable(ulBase,SPI_RX_DMA);
MAP_SPIDmaEnable(ulBase,SPI_TX_DMA);
MAP_SPIFIFOLevelSet(ulBase,1,1);
#if defined(SL_PLATFORM_MULTI_THREADED)
osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1);
MAP_SPIIntEnable(ulBase,SPI_INT_EOW);
osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1);
#else
MAP_IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler);
MAP_IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1);
MAP_IntEnable(INT_LSPI);
MAP_SPIIntEnable(ulBase,SPI_INT_EOW);
g_cDummy = 0x0;
#endif
}
MAP_SPIEnable(ulBase);
g_SpiFd = 1;
return g_SpiFd;
}