static int apbt_set_periodic(struct clock_event_device *evt) { struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ); u32 ctrl; pr_debug("%s CPU %d state=periodic\n", __func__, cpumask_first(evt->cpumask)); ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); ctrl |= APBTMR_CONTROL_MODE_PERIODIC; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); /* * DW APB p. 46, have to disable timer before load counter, * may cause sync problem. */ ctrl &= ~APBTMR_CONTROL_ENABLE; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); udelay(1); pr_debug("Setting clock period %lu for HZ %d\n", period, HZ); apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT); ctrl |= APBTMR_CONTROL_ENABLE; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); return 0; }
static int apbt_set_oneshot(struct clock_event_device *evt) { struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); u32 ctrl; pr_debug("%s CPU %d state=oneshot\n", __func__, cpumask_first(evt->cpumask)); ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); /* * set free running mode, this mode will let timer reload max * timeout which will give time (3min on 25MHz clock) to rearm * the next event, therefore emulate the one-shot mode. */ ctrl &= ~APBTMR_CONTROL_ENABLE; ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); /* write again to set free running mode */ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); /* * DW APB p. 46, load counter with all 1s before starting free * running mode. */ apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT); ctrl &= ~APBTMR_CONTROL_INT; ctrl |= APBTMR_CONTROL_ENABLE; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); return 0; }
static int apbt_resume(struct clock_event_device *evt) { struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); pr_debug("%s CPU %d state=resume\n", __func__, cpumask_first(evt->cpumask)); apbt_enable_int(&dw_ced->timer); return 0; }
static int apbt_shutdown(struct clock_event_device *evt) { struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); u32 ctrl; pr_debug("%s CPU %d state=shutdown\n", __func__, cpumask_first(evt->cpumask)); ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); ctrl &= ~APBTMR_CONTROL_ENABLE; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); return 0; }
static irqreturn_t dw_apb_clockevent_irq(int irq, void *data) { struct clock_event_device *evt = data; struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); if (!evt->event_handler) { pr_info("Spurious APBT timer interrupt %d", irq); return IRQ_NONE; } if (dw_ced->eoi) dw_ced->eoi(&dw_ced->timer); evt->event_handler(evt); return IRQ_HANDLED; }
static int apbt_next_event(unsigned long delta, struct clock_event_device *evt) { u32 ctrl; struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); /* Disable timer */ ctrl = apbt_readl_relaxed(&dw_ced->timer, APBTMR_N_CONTROL); ctrl &= ~APBTMR_CONTROL_ENABLE; apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); /* write new count */ apbt_writel_relaxed(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT); ctrl |= APBTMR_CONTROL_ENABLE; apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); return 0; }
static void apbt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { unsigned long ctrl; unsigned long period; struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); pr_debug("%s CPU %d mode=%d\n", __func__, first_cpu(*evt->cpumask), mode); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: period = DIV_ROUND_UP(dw_ced->timer.freq, HZ); ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); ctrl |= APBTMR_CONTROL_MODE_PERIODIC; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); /* * DW APB p. 46, have to disable timer before load counter, * may cause sync problem. */ ctrl &= ~APBTMR_CONTROL_ENABLE; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); udelay(1); pr_debug("Setting clock period %lu for HZ %d\n", period, HZ); apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT); ctrl |= APBTMR_CONTROL_ENABLE; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); break; case CLOCK_EVT_MODE_ONESHOT: ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); /* * set free running mode, this mode will let timer reload max * timeout which will give time (3min on 25MHz clock) to rearm * the next event, therefore emulate the one-shot mode. */ ctrl &= ~APBTMR_CONTROL_ENABLE; ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); /* write again to set free running mode */ apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); /* * DW APB p. 46, load counter with all 1s before starting free * running mode. */ apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT); ctrl &= ~APBTMR_CONTROL_INT; ctrl |= APBTMR_CONTROL_ENABLE; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); ctrl &= ~APBTMR_CONTROL_ENABLE; apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); break; case CLOCK_EVT_MODE_RESUME: apbt_enable_int(&dw_ced->timer); break; } }