/*
* When the summary IRQ is raised, any number of GPIO lines may be high.
* It is the job of the summary handler to find all those GPIO lines
* which have been set as summary IRQ lines and which are triggered,
* and to call their interrupt handlers.
*/
static void owl_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned long bank, gpio_in_bank, pending, gpioctl;
struct irq_chip *chip = irq_desc_get_chip(desc);
chained_irq_enter(chip, desc);
gpioctl = act_readl(INTC_GPIOCTL);
bank = irq - OWL_IRQ_GPIOA;
if (bank >= 0 && bank < 5) {
if (gpioctl & (1 << ((bank * 5)))) {
/* check pending status in one gpio bank */
pending = act_readl(GPIO_REG_INTC_PD(bank * 32));
while (pending != 0) {
gpio_in_bank = ffs(pending) - 1;
generic_handle_irq(owl_gpio_to_irq(
&owl_gpio_chip, bank * 32 + gpio_in_bank));
pending &= ~GPIO_BIT(gpio_in_bank);
}
}
}
chained_irq_exit(chip, desc);
}
static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
chained_irq_enter(chip, desc);
generic_handle_irq((int)desc->irq_data.handler_data);
chained_irq_exit(chip, desc);
}
static void s3c_irq_demux(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
struct s3c_irq_intc *intc = irq_data->intc;
struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
unsigned int n, offset, irq;
unsigned long src, msk;
/* we're using individual domains for the non-dt case
* and one big domain for the dt case where the subintc
* starts at hwirq number 32.
*/
offset = irq_domain_get_of_node(intc->domain) ? 32 : 0;
chained_irq_enter(chip, desc);
src = __raw_readl(sub_intc->reg_pending);
msk = __raw_readl(sub_intc->reg_mask);
src &= ~msk;
src &= irq_data->sub_bits;
while (src) {
n = __ffs(src);
src &= ~(1 << n);
irq = irq_find_mapping(sub_intc->domain, offset + n);
generic_handle_irq(irq);
}
chained_irq_exit(chip, desc);
}
static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, combiner_irq;
unsigned long status;
chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
spin_unlock(&irq_controller_lock);
status &= chip_data->irq_mask;
if (status == 0)
goto out;
combiner_irq = __ffs(status);
cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
if (unlikely(cascade_irq >= NR_IRQS))
do_bad_IRQ(cascade_irq, desc);
else
generic_handle_irq(cascade_irq);
out:
chained_irq_exit(chip, desc);
}
static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct gic_chip_data *chip_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, gic_irq;
unsigned long status;
chained_irq_enter(chip, desc);
raw_spin_lock(&irq_controller_lock);
status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
raw_spin_unlock(&irq_controller_lock);
gic_irq = (status & 0x3ff);
if (gic_irq == 1023)
goto out;
cascade_irq = gic_irq + chip_data->irq_offset;
if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
do_bad_IRQ(cascade_irq, desc);
else
generic_handle_irq(cascade_irq);
out:
chained_irq_exit(chip, desc);
}
static void rk30_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
struct rk30_gpio_bank *bank = irq_get_handler_data(irq);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned gpio_irq;
u32 isr, ilr;
unsigned pin;
unsigned unmasked = 0;
chained_irq_enter(chip, desc);
isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
ilr = __raw_readl(bank->regbase + GPIO_INTTYPE_LEVEL);
gpio_irq = gpio_to_irq(bank->chip.base);
while (isr) {
pin = fls(isr) - 1;
/* if gpio is edge triggered, clear condition
* before executing the hander so that we don't
* miss edges
*/
if (ilr & (1 << pin)) {
unmasked = 1;
chained_irq_exit(chip, desc);
}
generic_handle_irq(gpio_irq + pin);
isr &= ~(1 << pin);
}
if (!unmasked)
chained_irq_exit(chip, desc);
}
static void combiner_handle_cascade_irq(struct irq_desc *desc)
{
struct combiner_chip_data *chip_data = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq, combiner_irq;
unsigned long status;
chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
spin_unlock(&irq_controller_lock);
status &= chip_data->irq_mask;
if (status == 0)
goto out;
combiner_irq = chip_data->hwirq_offset + __ffs(status);
cascade_irq = irq_find_mapping(combiner_irq_domain, combiner_irq);
if (unlikely(!cascade_irq))
handle_bad_irq(desc);
else
generic_handle_irq(cascade_irq);
out:
chained_irq_exit(chip, desc);
}
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_data *idata = irq_desc_get_irq_data(desc);
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
void __iomem *pio = at91_gpio->regbase;
unsigned long isr;
int n;
chained_irq_enter(chip, desc);
for (;;) {
/* Reading ISR acks pending (edge triggered) GPIO interrupts.
* When there none are pending, we're finished unless we need
* to process multiple banks (like ID_PIOCDE on sam9263).
*/
isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
if (!isr) {
if (!at91_gpio->next)
break;
at91_gpio = at91_gpio->next;
pio = at91_gpio->regbase;
continue;
}
n = find_first_bit(&isr, BITS_PER_LONG);
while (n < BITS_PER_LONG) {
generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
}
}
chained_irq_exit(chip, desc);
/* now it may re-trigger */
}
static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
int i, j, mask;
unsigned val;
struct irq_chip *chip = irq_desc_get_chip(desc);
chained_irq_enter(chip, desc);
for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
val = __raw_readl(msm_chip->regs.int_status);
val &= msm_chip->int_enable[0];
while (val) {
mask = val & -val;
j = fls(mask) - 1;
/* printk("%s %08x %08x bit %d gpio %d irq %d\n",
__func__, v, m, j, msm_chip->chip.start + j,
FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
val &= ~mask;
generic_handle_irq(FIRST_GPIO_IRQ +
msm_chip->chip.base + j);
}
}
chained_irq_exit(chip, desc);
}
static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
chained_irq_enter(chip, desc);
exynos4_irq_demux_eint(IRQ_EINT(16));
exynos4_irq_demux_eint(IRQ_EINT(24));
chained_irq_exit(chip, desc);
}
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
u32 *irq_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
chained_irq_enter(chip, desc);
generic_handle_irq(*irq_data);
chained_irq_exit(chip, desc);
}
/*
* DB1200/PB1200 CPLD IRQ muxer
*/
static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
{
unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
struct irq_chip *chip = irq_desc_get_chip(d);
chained_irq_enter(chip, d);
generic_handle_irq(bcsr_csc_base + __ffs(bisr));
chained_irq_exit(chip, d);
}
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
u32 *irq_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
int eint_irq;
chained_irq_enter(chip, desc);
eint_irq = irq_find_mapping(irq_domain, *irq_data);
generic_handle_irq(eint_irq);
chained_irq_exit(chip, desc);
}
static void idu_cascade_isr(struct irq_desc *desc)
{
struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
struct irq_chip *core_chip = irq_desc_get_chip(desc);
irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;
chained_irq_enter(core_chip, desc);
generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
chained_irq_exit(core_chip, desc);
}
static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
u32 a16_23, a24_31;
chained_irq_enter(chip, desc);
a16_23 = exynos_irq_demux_eint(IRQ_EINT(16));
a24_31 = exynos_irq_demux_eint(IRQ_EINT(24));
chained_irq_exit(chip, desc);
if (!a16_23 && !a24_31)
do_bad_IRQ(irq, desc);
}
static void oxnas_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct oxnas_gpio_bank *bank = gpiochip_get_data(gc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long stat;
unsigned int pin;
chained_irq_enter(chip, desc);
stat = readl(bank->reg_base + IRQ_PENDING);
for_each_set_bit(pin, &stat, BITS_PER_LONG)
generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
chained_irq_exit(chip, desc);
}
static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
{
unsigned long pending;
int offset;
struct pl061_gpio *chip = irq_desc_get_handler_data(desc);
struct irq_chip *irqchip = irq_desc_get_chip(desc);
chained_irq_enter(irqchip, desc);
pending = readb(chip->base + GPIOMIS);
writeb(pending, chip->base + GPIOIC);
if (pending) {
for_each_set_bit(offset, &pending, PL061_GPIO_NR)
generic_handle_irq(pl061_to_irq(&chip->gc, offset));
}
chained_irq_exit(irqchip, desc);
}
static void mx25_tsadc_irq_handler(struct irq_desc *desc)
{
struct mx25_tsadc *tsadc = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
u32 status;
chained_irq_enter(chip, desc);
regmap_read(tsadc->regs, MX25_TSC_TGSR, &status);
if (status & MX25_TGSR_GCQ_INT)
generic_handle_irq(irq_find_mapping(tsadc->domain, 1));
if (status & MX25_TGSR_TCQ_INT)
generic_handle_irq(irq_find_mapping(tsadc->domain, 0));
chained_irq_exit(chip, desc);
}
static void goldfish_pic_cascade(struct irq_desc *desc)
{
struct goldfish_pic_data *gfpic = irq_desc_get_handler_data(desc);
struct irq_chip *host_chip = irq_desc_get_chip(desc);
u32 pending, hwirq, virq;
chained_irq_enter(host_chip, desc);
pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING);
while (pending) {
hwirq = __fls(pending);
virq = irq_linear_revmap(gfpic->irq_domain, hwirq);
generic_handle_irq(virq);
pending &= ~(1 << hwirq);
}
chained_irq_exit(host_chip, desc);
}
static void ftgpio_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct ftgpio_gpio *g = gpiochip_get_data(gc);
struct irq_chip *irqchip = irq_desc_get_chip(desc);
int offset;
unsigned long stat;
chained_irq_enter(irqchip, desc);
stat = readl(g->base + GPIO_INT_STAT_RAW);
if (stat)
for_each_set_bit(offset, &stat, gc->ngpio)
generic_handle_irq(irq_find_mapping(gc->irq.domain,
offset));
chained_irq_exit(irqchip, desc);
}
static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
u32 status)
{
struct nmk_gpio_chip *nmk_chip;
struct irq_chip *host_chip = irq_get_chip(irq);
unsigned int first_irq;
chained_irq_enter(host_chip, desc);
nmk_chip = irq_get_handler_data(irq);
first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
while (status) {
int bit = __ffs(status);
generic_handle_irq(first_irq + bit);
status &= ~BIT(bit);
}
chained_irq_exit(host_chip, desc);
}
static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
u32 status)
{
struct nmk_gpio_chip *nmk_chip;
struct irq_chip *host_chip = irq_get_chip(irq);
unsigned int first_irq;
chained_irq_enter(host_chip, desc);
nmk_chip = irq_get_handler_data(irq);
first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
while (status) {
int bit = __ffs(status);
generic_handle_irq(first_irq + bit);
status &= ~BIT(bit);
}
chained_irq_exit(host_chip, desc);
}
/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
* are consecutive when looking up the interrupt in the demux routines.
*/
static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
{
struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
int base = uirq->base_irq;
struct irq_chip *chip = irq_get_chip(irq);
chained_irq_enter(chip, desc);
if (pend & (1 << 0))
generic_handle_irq(base);
if (pend & (1 << 1))
generic_handle_irq(base + 1);
if (pend & (1 << 2))
generic_handle_irq(base + 2);
if (pend & (1 << 3))
generic_handle_irq(base + 3);
chained_irq_exit(chip, desc);
}
static void rps_handle_cascade_irq(struct irq_desc *desc)
#endif
{
struct rps_chip_data *chip_data = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq, rps_irq;
u32 status;
chained_irq_enter(chip, desc);
status = ioread32(chip_data->base + RPS_STATUS);
rps_irq = __ffs(status);
cascade_irq = irq_find_mapping(chip_data->domain, rps_irq);
if (unlikely(rps_irq >= RPS_IRQ_COUNT))
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
handle_bad_irq(cascade_irq, desc);
#else
handle_bad_irq(desc);
#endif
else
static void gpio_irq_handler(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
struct davinci_gpio_regs __iomem *g;
u32 mask = 0xffff;
struct davinci_gpio_controller *d;
d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
g = (struct davinci_gpio_regs __iomem *)d->regs;
/* we only care about one bank */
if (irq & 1)
mask <<= 16;
/* temporarily mask (level sensitive) parent IRQ */
chained_irq_enter(irq_desc_get_chip(desc), desc);
while (1) {
u32 status;
int bit;
/* ack any irqs */
status = readl_relaxed(&g->intstat) & mask;
if (!status)
break;
writel_relaxed(status, &g->intstat);
/* now demux them to the right lowlevel handler */
while (status) {
bit = __ffs(status);
status &= ~BIT(bit);
generic_handle_irq(
irq_find_mapping(d->irq_domain,
d->chip.base + bit));
}
}
chained_irq_exit(irq_desc_get_chip(desc), desc);
/* now it may re-trigger */
}
static void imx_msi_handler(unsigned int irq, struct irq_desc *desc)
{
int i, j;
unsigned int status;
struct irq_chip *chip = irq_get_chip(irq);
unsigned int base_irq = IRQ_IMX_MSI_0;
chained_irq_enter(chip, desc);
for (i = 0; i < 8; i++) {
status = imx_pcie_msi_pending(i);
while (status) {
j = __fls(status);
generic_handle_irq(base_irq + j);
status &= ~(1 << j);
}
base_irq += 32;
}
if (intd_active) {
pr_info("%s intd\n", __func__);
generic_handle_irq(MXC_INT_PCIE_0B);
}
chained_irq_exit(chip, desc);
}
/**
* xgpiops_irqhandler - IRQ handler for the gpio banks of a gpio device
* @irq: irq number of the gpio bank where interrupt has occurred
* @desc: irq descriptor instance of the 'irq'
*
* This function reads the Interrupt Status Register of each bank to get the
* gpio pin number which has triggered an interrupt. It then acks the triggered
* interrupt and calls the pin specific handler set by the higher layer
* application for that pin.
* Note: A bug is reported if no handler is set for the gpio pin.
*/
void xgpiops_irqhandler(unsigned int irq, struct irq_desc *desc)
{
int gpio_irq = (int)irq_get_handler_data(irq);
struct xgpiops *gpio = (struct xgpiops *)irq_get_chip_data(gpio_irq);
unsigned int int_sts, int_enb, bank_num;
struct irq_desc *gpio_irq_desc;
struct irq_chip *chip = irq_desc_get_chip(desc);
chained_irq_enter(chip, desc);
for (bank_num = 0; bank_num < 4; bank_num++) {
int_sts = xgpiops_readreg(gpio->base_addr +
XGPIOPS_INTSTS_OFFSET(bank_num));
int_enb = xgpiops_readreg(gpio->base_addr +
XGPIOPS_INTMASK_OFFSET(bank_num));
int_sts &= ~int_enb;
for (; int_sts != 0; int_sts >>= 1, gpio_irq++) {
if ((int_sts & 1) == 0)
continue;
gpio_irq_desc = irq_to_desc(gpio_irq);
BUG_ON(!gpio_irq_desc);
chip = irq_desc_get_chip(gpio_irq_desc);
BUG_ON(!chip);
chip->irq_ack(&gpio_irq_desc->irq_data);
/* call the pin specific handler */
generic_handle_irq(gpio_irq);
}
/* shift to first virtual irq of next bank */
gpio_irq = (int)irq_get_handler_data(irq) +
(xgpiops_pin_table[bank_num] + 1);
}
chip = irq_desc_get_chip(desc);
chained_irq_exit(chip, desc);
}
/**
* zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
* @irq: irq number of the gpio bank where interrupt has occurred
* @desc: irq descriptor instance of the 'irq'
*
* This function reads the Interrupt Status Register of each bank to get the
* gpio pin number which has triggered an interrupt. It then acks the triggered
* interrupt and calls the pin specific handler set by the higher layer
* application for that pin.
* Note: A bug is reported if no handler is set for the gpio pin.
*/
static void zynq_gpio_irqhandler(unsigned int irq, struct irq_desc *desc)
{
struct zynq_gpio *gpio = (struct zynq_gpio *)irq_get_handler_data(irq);
int gpio_irq = gpio->irq_base;
unsigned int int_sts, int_enb, bank_num;
struct irq_desc *gpio_irq_desc;
struct irq_chip *chip = irq_desc_get_chip(desc);
chained_irq_enter(chip, desc);
for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++) {
int_sts = zynq_gpio_readreg(gpio->base_addr +
ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
int_enb = zynq_gpio_readreg(gpio->base_addr +
ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
int_sts &= ~int_enb;
for (; int_sts != 0; int_sts >>= 1, gpio_irq++) {
if (!(int_sts & 1))
continue;
gpio_irq_desc = irq_to_desc(gpio_irq);
BUG_ON(!gpio_irq_desc);
chip = irq_desc_get_chip(gpio_irq_desc);
BUG_ON(!chip);
chip->irq_ack(&gpio_irq_desc->irq_data);
/* call the pin specific handler */
generic_handle_irq(gpio_irq);
}
/* shift to first virtual irq of next bank */
gpio_irq = gpio->irq_base + zynq_gpio_pin_table[bank_num] + 1;
}
chip = irq_desc_get_chip(desc);
chained_irq_exit(chip, desc);
}
/*
* xgold cascade handler entry
*/
void xgold_irq_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct xgold_irq_chip_data *data = NULL;
struct irq_domain *domain = NULL;
struct irq_chip *chip = irq_get_chip(irq);
uint32_t casc_irq = 0;
int32_t domain_irq = 0;
data = irq_get_handler_data(irq);
if (!data || !chip)
return;
domain = data->domain;
chained_irq_enter(chip, desc);
domain_irq = xgold_irq_find_mapping(irq, data->type);
if (domain_irq >= 0)
casc_irq = irq_find_mapping(data->domain, domain_irq);
if (data->handle_entry)
data->handle_entry(data);
if (casc_irq > 0)
generic_handle_irq(casc_irq);
if (data->handle_exit)
data->handle_exit(data);
chained_irq_exit(chip, desc);
return;
}
