uint32 cdp_cmd(UNIT * uptr, uint16 cmd, uint16 dev)
{
int chan = UNIT_G_CHAN(uptr->flags);
int u = (uptr - cdp_unit);
extern uint16 IC;
if ((uptr->flags & UNIT_ATT) != 0 && cmd == IO_WRS) {
/* Start device */
if (!(uptr->u5 & CDPSTA_CMD)) {
dev_pulse[chan] &= ~PUNCH_M;
uptr->u5 &= ~CDPSTA_PUNCH;
if ((uptr->u5 & CDPSTA_ON) == 0) {
uptr->wait = 330; /* Startup delay */
} else if (uptr->u5 & CDPSTA_IDLE && uptr->wait <= 30) {
uptr->wait += 85; /* Wait for next latch point */
}
uptr->u5 |= (CDPSTA_WRITE | CDPSTA_CMD);
uptr->u5 &= ~CDPSTA_POSMASK;
chan_set_sel(chan, 1);
chan_clear_status(chan);
sim_activate(uptr, us_to_ticks(1000)); /* activate */
sim_debug(DEBUG_CMD, &cdp_dev, "%05o WRS unit=%d\n", IC, u);
return SCPE_OK;
}
}
chan_set_attn(chan);
return SCPE_IOERR;
}
/*
* Device entry points for card reader.
*/
uint32 cdr_cmd(UNIT * uptr, uint16 cmd, uint16 dev)
{
int chan = UNIT_G_CHAN(uptr->flags);
int u = (uptr - cdr_unit);
int stk = dev & 017;
/* Are we currently tranfering? */
if (uptr->u5 & URCSTA_READ)
return SCPE_BUSY;
/* Test ready */
if (cmd == IO_TRS && uptr->flags & UNIT_ATT) {
sim_debug(DEBUG_CMD, &cdr_dev, "%d: Test Rdy\n", u);
return SCPE_OK;
}
if (stk == 10)
stk = 0;
#ifdef STACK_DEV
uptr->u5 &= ~0xF0000;
uptr->u5 |= stk << 16;
#endif
if (uptr->u5 & (URCSTA_EOF|URCSTA_ERR))
return SCPE_IOERR;
/* Process commands */
switch(cmd) {
case IO_RDS:
sim_debug(DEBUG_CMD, &cdr_dev, "%d: Cmd RDS %02o\n", u, dev & 077);
#ifdef I7010
if (stk!= 9)
#endif
uptr->u5 &= ~(URCSTA_CARD|URCSTA_ERR);
break;
case IO_CTL:
sim_debug(DEBUG_CMD, &cdr_dev, "%d: Cmd CTL %02o\n", u, dev & 077);
#ifdef I7010
uptr->u5 |= URCSTA_NOXFER;
#endif
break;
default:
chan_set_attn(chan);
return SCPE_IOERR;
}
/* If at eof, just return EOF */
if (uptr->u5 & URCSTA_EOF) {
chan_set_eof(chan);
chan_set_attn(chan);
return SCPE_OK;
}
uptr->u5 |= URCSTA_READ;
uptr->u4 = 0;
if ((uptr->u5 & URCSTA_NOXFER) == 0)
chan_set_sel(chan, 0);
/* Wake it up if not busy */
if ((uptr->u5 & URCSTA_BUSY) == 0)
sim_activate(uptr, 50);
return SCPE_OK;
}
