void updatePosition(int row, int col, int diff) {
for (int i = row; i <= n; i += changeBit(i)) {
for (int j = col; j <= m; j += changeBit(j)) {
sum[i][j] += diff;
}
}
}
int sumRange(int row, int col) {
int ans = 0;
for (int i = row; i >= 1; i -= changeBit(i)) {
for (int j = col; j >= 1; j -= changeBit(j)) {
ans += sum[i][j];
}
}
return ans;
}
/* Enable the compare function: A conversion will be completed only when the ADC value
* is >= compValue (greaterThan=1) or < compValue (greaterThan=0)
* Call it after changing the resolution
* Use with interrupts or poll conversion completion with isADC_Complete()
*/
void ADC_Module::enableCompare(int16_t compValue, bool greaterThan) {
if (calibrating) wait_for_cal(); // if we modify the adc's registers when calibrating, it will fail
// *ADC_SC2_cfe = 1; // enable compare
// *ADC_SC2_cfgt = (int32_t)greaterThan; // greater or less than?
setBit(ADC_SC2, ADC_SC2_ACFE_BIT);
changeBit(ADC_SC2, ADC_SC2_ACFGT_BIT, greaterThan);
*ADC_CV1 = (int16_t)compValue; // comp value
}
extern "C" int main()
{
auto input = generateInput();
for(const auto x: input) {
std::cout << x << std::endl;
}
auto start = std::chrono::high_resolution_clock::now();
for(const auto num: input)
{
changeBit(bitmapArray, num, 1);
}
auto output = generateBit(bitmapArray);
for(int i =0; i<10; i++) {
std::cout << output[i] << " ";
}
auto end = std::chrono::high_resolution_clock::now();
std::cout << (end - start).count();
return 0;
}
/*
* \param speed can be ADC_VERY_LOW_SPEED, ADC_LOW_SPEED, ADC_MED_SPEED, ADC_HIGH_SPEED_16BITS, ADC_HIGH_SPEED or ADC_VERY_HIGH_SPEED
ADC_VERY_LOW_SPEED is guaranteed to be the lowest possible speed within specs for resolutions less than 16 bits (higher than 1 MHz),
it's different from ADC_LOW_SPEED only for 24, 4 or 2 MHz.
ADC_LOW_SPEED is guaranteed to be the lowest possible speed within specs for all resolutions (higher than 2 MHz).
ADC_MED_SPEED is always >= ADC_LOW_SPEED and <= ADC_HIGH_SPEED.
ADC_HIGH_SPEED_16BITS is guaranteed to be the highest possible speed within specs for all resolutions (lower or eq than 12 MHz).
ADC_HIGH_SPEED is guaranteed to be the highest possible speed within specs for resolutions less than 16 bits (lower or eq than 18 MHz).
ADC_VERY_HIGH_SPEED may be out of specs, it's different from ADC_HIGH_SPEED only for 48, 40 or 24 MHz.
* It doesn't recalibrate at the end.
*/
void ADC_Module::setConversionSpeed(uint8_t speed) {
if(speed==conversion_speed) { // no change
return;
}
if (calibrating) wait_for_cal();
// internal asynchronous clock settings: fADK = 2.4, 4.0, 5.2 or 6.2 MHz
if(speed >= ADC_ADACK_2_4) {
setBit(ADC_CFG2, ADC_CFG2_ADACKEN_BIT); // enable ADACK (takes max 5us to be ready)
setBit(ADC_CFG1, ADC_CFG1_ADICLK1_BIT); // select ADACK as clock source
setBit(ADC_CFG1, ADC_CFG1_ADICLK0_BIT);
clearBit(ADC_CFG1, ADC_CFG1_ADIV0_BIT); // select divider 1
clearBit(ADC_CFG1, ADC_CFG1_ADIV1_BIT); // we could divide this clk, but it would be too small for ADC use.
if(speed == ADC_ADACK_2_4) {
clearBit(ADC_CFG2, ADC_CFG2_ADHSC_BIT);
setBit(ADC_CFG1, ADC_CFG1_ADLPC_BIT);
} else if(speed == ADC_ADACK_4_0) {
setBit(ADC_CFG2, ADC_CFG2_ADHSC_BIT);
setBit(ADC_CFG1, ADC_CFG1_ADLPC_BIT);
} else if(speed == ADC_ADACK_5_2) {
clearBit(ADC_CFG2, ADC_CFG2_ADHSC_BIT);
clearBit(ADC_CFG1, ADC_CFG1_ADLPC_BIT);
} else if(speed == ADC_ADACK_6_2) {
setBit(ADC_CFG2, ADC_CFG2_ADHSC_BIT);
clearBit(ADC_CFG1, ADC_CFG1_ADLPC_BIT);
}
conversion_speed = speed;
return;
}
// normal bus clock used
// *ADC_CFG2_adacken = 0; // disable the internal asynchronous clock
clearBit(ADC_CFG2, ADC_CFG2_ADACKEN_BIT);
uint32_t ADC_CFG1_speed; // store the clock and divisor
if(speed == ADC_VERY_LOW_SPEED) {
// *ADC_CFG2_adhsc = 0; // no high-speed config
// *ADC_CFG1_adlpc = 1; // use low power conf.
clearBit(ADC_CFG2, ADC_CFG2_ADHSC_BIT);
setBit(ADC_CFG1, ADC_CFG1_ADLPC_BIT);
ADC_CFG1_speed = ADC_CFG1_VERY_LOW_SPEED;
} else if(speed == ADC_LOW_SPEED) {
// *ADC_CFG2_adhsc = 0; // no high-speed config
// *ADC_CFG1_adlpc = 1; // use low power conf.
clearBit(ADC_CFG2, ADC_CFG2_ADHSC_BIT);
setBit(ADC_CFG1, ADC_CFG1_ADLPC_BIT);
ADC_CFG1_speed = ADC_CFG1_LOW_SPEED;
} else if(speed == ADC_MED_SPEED) {
// *ADC_CFG2_adhsc = 0; // no high-speed config
// *ADC_CFG1_adlpc = 0; // no low power conf.
clearBit(ADC_CFG2, ADC_CFG2_ADHSC_BIT);
clearBit(ADC_CFG1, ADC_CFG1_ADLPC_BIT);
ADC_CFG1_speed = ADC_CFG1_MED_SPEED;
} else if(speed == ADC_HIGH_SPEED_16BITS) {
// *ADC_CFG2_adhsc = 1; // high-speed config: add 2 ADCK
// *ADC_CFG1_adlpc = 0; // no low power conf.
setBit(ADC_CFG2, ADC_CFG2_ADHSC_BIT);
clearBit(ADC_CFG1, ADC_CFG1_ADLPC_BIT);
ADC_CFG1_speed = ADC_CFG1_HI_SPEED_16_BITS;
} else if(speed == ADC_HIGH_SPEED) {
// *ADC_CFG2_adhsc = 1; // high-speed config: add 2 ADCK
// *ADC_CFG1_adlpc = 0; // no low power conf.
setBit(ADC_CFG2, ADC_CFG2_ADHSC_BIT);
clearBit(ADC_CFG1, ADC_CFG1_ADLPC_BIT);
ADC_CFG1_speed = ADC_CFG1_HI_SPEED;
} else if(speed == ADC_VERY_HIGH_SPEED) { // this speed is most likely out of specs, so accurancy can be bad
// *ADC_CFG2_adhsc = 1; // high-speed config: add 2 ADCK
// *ADC_CFG1_adlpc = 0; // no low power conf.
setBit(ADC_CFG2, ADC_CFG2_ADHSC_BIT);
clearBit(ADC_CFG1, ADC_CFG1_ADLPC_BIT);
ADC_CFG1_speed = ADC_CFG1_VERY_HIGH_SPEED;
} else {
fail_flag |= ADC_ERROR_OTHER;
return;
}
// clock source is bus or bus/2
// *ADC_CFG1_adiclk1 = !!(ADC_CFG1_speed & ADC_CFG1_ADICLK_MASK_1); // !!x converts the number x to either 0 or 1.
// *ADC_CFG1_adiclk0 = !!(ADC_CFG1_speed & ADC_CFG1_ADICLK_MASK_0);
changeBit(ADC_CFG1, ADC_CFG1_ADICLK1_BIT, !!(ADC_CFG1_speed & ADC_CFG1_ADICLK_MASK_1));
changeBit(ADC_CFG1, ADC_CFG1_ADICLK0_BIT, !!(ADC_CFG1_speed & ADC_CFG1_ADICLK_MASK_0));
// divisor for the clock source: 1, 2, 4 or 8.
// so total speed can be: bus, bus/2, bus/4, bus/8 or bus/16.
// *ADC_CFG1_adiv1 = !!(ADC_CFG1_speed & ADC_CFG1_ADIV_MASK_1);
// *ADC_CFG1_adiv0 = !!(ADC_CFG1_speed & ADC_CFG1_ADIV_MASK_0);
changeBit(ADC_CFG1, ADC_CFG1_ADIV1_BIT, !!(ADC_CFG1_speed & ADC_CFG1_ADIV_MASK_1));
changeBit(ADC_CFG1, ADC_CFG1_ADIV0_BIT, !!(ADC_CFG1_speed & ADC_CFG1_ADIV_MASK_0));
conversion_speed = speed;
}
