static void chb_radio_init() { U8 ieee_addr[8]; // reset chip chb_reset(); // disable intps while we config the radio chb_reg_write(IRQ_MASK, 0); // force transceiver off while we configure the intps chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F); // make sure the transceiver is in the off state before proceeding while ((chb_reg_read(TRX_STATUS) & 0x1f) != TRX_OFF); // set radio cfg parameters // **note** uncomment if these will be set to something other than default //chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS); //chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS); //chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS); //chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0); //chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS); //chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES); // set frame version that we'll accept chb_reg_read_mod_write(CSMA_SEED_1, CHB_FRM_VER << CHB_FVN_POS, 3 << CHB_FVN_POS); // set interrupt mask // re-enable intps while we config the radio chb_reg_write(IRQ_MASK, (1<<IRQ_RX_START) | (1<<IRQ_TRX_END)); #if (CFG_CHIBI_PROMISCUOUS == 0) // set autocrc mode chb_reg_read_mod_write(TRX_CTRL_1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS); #endif // set up default phy modulation, data rate and power (Ex. OQPSK, 100 kbps, 868 MHz, 3dBm) chb_set_mode(CFG_CHIBI_MODE); // Defined in projectconfig.h chb_set_pwr(CFG_CHIBI_POWER); // Defined in projectconfig.h chb_set_channel(CFG_CHIBI_CHANNEL); // Defined in projectconfig.h // set fsm state // put trx in rx auto ack mode chb_set_state(RX_STATE); // set pan ID chb_reg_write16(PAN_ID_0, CFG_CHIBI_PANID); // Defined in projectconfig.h // set short addr // NOTE: Possibly get this from EEPROM chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr()); // set long addr // NOTE: Possibly get this from EEPROM chb_get_ieee_addr(ieee_addr); chb_reg_write64(IEEE_ADDR_0, ieee_addr); #if (CHB_CC1190_PRESENT) // set high gain mode pin to output and init to zero gpioSetDir (CHB_CC1190_HGM_PORT, CHB_CC1190_HGM_PIN, 1); gpioSetPullup (&CHB_CC1190_HGM_IOCONREG, gpioPullupMode_Inactive); gpioSetValue (CHB_CC1190_HGM_PORT, CHB_CC1190_HGM_PIN, 0); // set external power amp on AT86RF212 chb_reg_read_mod_write(TRX_CTRL_1, 1<<CHB_PA_EXT_EN_POS, 1<<CHB_PA_EXT_EN_POS); // set power to lowest level possible chb_set_pwr(0xd); // set to -11 dBm #endif // set interrupt/gpio pin to input gpioSetDir (CHB_EINTPORT, CHB_EINTPIN, 0); // set internal resistor on EINT pin to inactive gpioSetPullup (&CHB_EINTPIN_IOCONREG, gpioPullupMode_Inactive); // configure pin for interrupt gpioSetInterrupt (CHB_EINTPORT, CHB_EINTPIN, gpioInterruptSense_Edge, // Edge-sensitive gpioInterruptEdge_Single, // Single edge gpioInterruptEvent_ActiveHigh); // High triggers interrupt // enable interrupt gpioIntEnable (CHB_EINTPORT, CHB_EINTPIN); if (chb_get_state() != RX_STATE) { // ERROR occurred initializing the radio. Print out error message. printf(chb_err_init); } }
static error_t chb_radio_init() { U8 ieee_addr[8]; // reset chip (this can fail if there is a HW or config problem) error_t error = chb_reset(); if (error) { return error; } // disable intps while we config the radio chb_reg_write(IRQ_MASK, 0); // force transceiver off while we configure the intps chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F); // make sure the transceiver is in the off state before proceeding while ((chb_reg_read(TRX_STATUS) & 0x1f) != TRX_OFF); // set radio cfg parameters // **note** uncomment if these will be set to something other than default //chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS); //chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS); //chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS); //chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0); //chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS); //chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES); // set frame version that we'll accept chb_reg_read_mod_write(CSMA_SEED_1, CHB_FRM_VER << CHB_FVN_POS, 3 << CHB_FVN_POS); // set interrupt mask // re-enable intps while we config the radio chb_reg_write(IRQ_MASK, (1<<IRQ_RX_START) | (1<<IRQ_TRX_END)); #if (CFG_CHIBI_PROMISCUOUS == 0) // set autocrc mode chb_reg_read_mod_write(TRX_CTRL_1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS); #endif // set up default phy modulation, data rate and power (Ex. OQPSK, 100 kbps, 868 MHz, 3dBm) chb_set_mode(CFG_CHIBI_MODE); // Defined in projectconfig.h chb_set_pwr(CFG_CHIBI_POWER); // Defined in projectconfig.h chb_set_channel(CFG_CHIBI_CHANNEL); // Defined in projectconfig.h // set fsm state // put trx in rx auto ack mode chb_set_state(RX_STATE); // set pan ID chb_reg_write16(PAN_ID_0, CFG_CHIBI_PANID); // Defined in projectconfig.h // set short addr // NOTE: Possibly get this from EEPROM chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr()); // set long addr // NOTE: Possibly get this from EEPROM chb_get_ieee_addr(ieee_addr); chb_reg_write64(IEEE_ADDR_0, ieee_addr); #if (CHB_CC1190_PRESENT) // set high gain mode pin to output and init to zero GPIOSetDir(CFG_CHIBI_CC1190_HGM_PORT, CFG_CHIBI_CC1190_HGM_PIN, 1); GPIOSetBitValue(CFG_CHIBI_CC1190_HGM_PORT, CFG_CHIBI_CC1190_HGM_PIN, 0); // set external power amp on AT86RF212 chb_reg_read_mod_write(TRX_CTRL_1, 1<<CHB_PA_EXT_EN_POS, 1<<CHB_PA_EXT_EN_POS); // set power to lowest level possible chb_set_pwr(0xd); // set to -11 dBm #endif // set interrupt/gpio pin to input GPIOSetDir(CFG_CHIBI_EINTPORT, CFG_CHIBI_EINTPIN, 0); // Channel 0, sense (0=edge, 1=level), polarity (0=low/falling, 1=high/rising) GPIOSetPinInterrupt( 0, CFG_CHIBI_EINTPORT, CFG_CHIBI_EINTPIN, 0, 1 ); // Enable interrupt // GPIOPinIntEnable( 0, 0 ); if (chb_get_state() != RX_STATE) { // ERROR occurred initializing the radio. Print out error message. printf(chb_err_init); return ERROR_DEVICENOTINITIALISED; } return ERROR_NONE; }
static void chb_radio_init() { U8 ieee_addr[8]; // reset chip chb_reset(); // disable intps while we config the radio chb_reg_write(IRQ_MASK, 0); // force transceiver off while we configure the intps chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F); // make sure the transceiver is in the off state before proceeding while ((chb_reg_read(TRX_STATUS) & 0x1f) != TRX_OFF); // set radio cfg parameters // **note** uncomment if these will be set to something other than default //chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS); //chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS); //chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS); //chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0); //chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS); //chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES); // set frame version that we'll accept chb_reg_read_mod_write(CSMA_SEED_1, CHB_FRM_VER << CHB_FVN_POS, 3 << CHB_FVN_POS); // set interrupt mask // re-enable intps while we config the radio chb_reg_write(IRQ_MASK, (1<<IRQ_RX_START) | (1<<IRQ_TRX_END)); // set autocrc mode chb_reg_read_mod_write(TRX_CTRL_1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS); // set up default phy modulation and data rate - OQPSK, 250 kbps, 915 MHz chb_set_mode(CHB_INIT_MODE); chb_set_channel(CHB_CHANNEL); // set fsm state // put trx in rx auto ack mode chb_set_state(RX_AACK_ON); // set pan ID chb_reg_write16(PAN_ID_0, CHB_PAN_ID); // set short addr // NOTE: Possibly get this from EEPROM chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr()); // set long addr // NOTE: Possibly get this from EEPROM chb_get_ieee_addr(ieee_addr); chb_reg_write64(IEEE_ADDR_0, ieee_addr); // enable mcu intp pin on INT4 CFG_CHB_INTP_RISE_EDGE(); while (chb_get_state() != RX_AACK_ON); }
static void chb_radio_init() { U8 ieee_addr[8]; U8 part_num; // disable intps while we config the radio chb_reg_write(IRQ_MASK, 0); // force transceiver off while we configure the intps chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F); chb_delay_us(TIME_P_ON_TO_TRX_OFF); // set radio cfg parameters // **note** uncomment if these will be set to something other than default //chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS); //chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS); //chb_reg_read_mod_write(CSMA_SEED_1, CHB_MIN_BE << CHB_MIN_BE_POS, 0x3 << CHB_MIN_BE_POS); //chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS); //chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0); //chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS); //chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES); //chb_reg_read_mod_write(PHY_TX_PWR, CHB_TX_PWR, 0xf); // identify device part_num = chb_reg_read(PART_NUM); switch (part_num) { case CHB_AT86RF230: // set default channel chb_set_channel(CHB_2_4GHZ_DEFAULT_CHANNEL); #if (CHIBI_PROMISCUOUS == 0) // set autocrc mode chb_reg_read_mod_write(PHY_TX_PWR, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS); #endif break; case CHB_AT86RF231: // set default channel chb_set_channel(CHB_2_4GHZ_DEFAULT_CHANNEL); #if (CHIBI_PROMISCUOUS == 0) // set autocrc mode chb_reg_read_mod_write(PHY_TX_PWR, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS); #endif break; case CHB_AT86RF212: // set mode to OQPSK or BPSK depending on setting chb_set_mode(CHB_INIT_MODE); // set default channel and tx power to max chb_set_channel(CHB_900MHZ_DEFAULT_CHANNEL); chb_reg_read_mod_write(PHY_TX_PWR, CHB_900MHZ_TX_PWR, 0xf); #if (CHIBI_PROMISCUOUS == 0) // set autocrc mode chb_reg_read_mod_write(TRX_CTRL1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS); #endif break; default: Serial.print("ERROR: Unknown radio detected.\n"); break; } // set transceiver's fsm state chb_set_state(RX_STATE); // set pan ID chb_reg_write16(PAN_ID_0, CHB_PAN_ID); // set short addr // NOTE: Possibly get this from EEPROM chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr()); // set long addr // NOTE: Possibly get this from EEPROM chb_get_ieee_addr(ieee_addr); chb_reg_write64(IEEE_ADDR_0, ieee_addr); // do a read of the interrupt register to clear the interrupt bits chb_reg_read(IRQ_STATUS); // re-enable intps while we config the radio chb_reg_write(IRQ_MASK, 0x8); // enable mcu intp pin on INT6 for rising edge CFG_CHB_INTP(); if (chb_get_state() != RX_STATE) { // ERROR occurred initializing the radio. Print out error message. char buf[50]; // grab the error message from flash & print it out strcpy_P(buf, chb_err_init); Serial.print(buf); } }
static void chb_radio_init() { U8 ieee_addr[8]; // reset chip chb_reset(); // disable intps while we config the radio chb_reg_write(IRQ_MASK, 0); // force transceiver off while we configure the intps chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F); // make sure the transceiver is in the off state before proceeding while ((chb_reg_read(TRX_STATUS) & 0x1f) != CHB_TRX_OFF); // set radio cfg parameters // **note** uncomment if these will be set to something other than default //chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS); //chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS); //chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS); //chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0); //chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS); //chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES); // set frame version that we'll accept chb_reg_read_mod_write(CSMA_SEED_1, CHB_FRM_VER << CHB_FVN_POS, 3 << CHB_FVN_POS); // set interrupt mask // re-enable intps while we config the radio chb_reg_write(IRQ_MASK, (1<<IRQ_RX_START) | (1<<IRQ_TRX_END)); #if (CHB_PROMISCUOUS == 0) // set autocrc mode chb_reg_read_mod_write(TRX_CTRL_1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS); #endif // set up default phy modulation and data rate - OQPSK, 250 kbps, 915 MHz chb_set_mode(CHB_INIT_MODE); chb_set_channel(CHB_CHANNEL); // set fsm state // put trx in rx auto ack mode chb_set_state(RX_STATE); // set pan ID chb_reg_write16(PAN_ID_0, CHB_PAN_ID); // set short addr // NOTE: Possibly get this from EEPROM chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr()); // set long addr // NOTE: Possibly get this from EEPROM chb_get_ieee_addr(ieee_addr); chb_reg_write64(IEEE_ADDR_0, ieee_addr); #if (CHB_CC1190_PRESENT) // set high gain mode pin to output and init to zero CHB_CC1190_HGM_DDIR |= 1<<CHB_CC1190_HGM_PIN; CHB_CC1190_HGM_PORT &= ~(1<<CHB_CC1190_HGM_PIN); // set external power amp on AT86RF212 chb_reg_read_mod_write(TRX_CTRL_1, 1<<CHB_PA_EXT_EN_POS, 1<<CHB_PA_EXT_EN_POS); // set power to 0 dBm if CC1190 is being used. chb_set_pwr(0x24); #endif // enable mcu intp pin CFG_CHB_INTP_RISE_EDGE(); if (chb_get_state() != RX_STATE) { // ERROR occurred initializing the radio. Print out error message. char buf[50]; // grab the error message from flash & print it out strcpy_P(buf, chb_err_init); printf(buf); } }