U8 chb_tx(U8 *hdr, U8 *data, U8 len)
{
U8 state = chb_get_state();
chb_pcb_t *pcb = chb_get_pcb();
if ((state == BUSY_TX) || (state == BUSY_TX_ARET))
{
return RADIO_WRONG_STATE;
}
// TODO: check why we need to transition to the off state before we go to tx_aret_on
chb_set_state(TRX_OFF);
chb_set_state(TX_ARET_ON);
// TODO: try and start the frame transmission by writing TX_START command instead of toggling
// sleep pin...i just feel like it's kind of weird...
// write frame to buffer. first write header into buffer (add 1 for len byte), then data.
chb_frame_write(hdr, CHB_HDR_SZ + 1, data, len);
//Do frame transmission
chb_reg_read_mod_write(TRX_STATE, CMD_TX_START, 0x1F);
// wait for the transmission to end, signalled by the TRX END flag
while (!pcb->tx_end);
pcb->tx_end = false;
// check the status of the transmission
return chb_get_status();
}
void chb_sleep(U8 enb)
{
if (enb)
{
// first we need to go to TRX OFF state
chb_set_state(TRX_OFF);
// then we need to make SLP_TR pin an input. this enables the external
// pullup on that pin. we do this so that we won't need to go through
// a voltage divider which drains current. we want to avoid that when
// we sleep
CHB_SLPTR_DDIR &= ~(_BV(CHB_SLPTR_PIN));
}
else
{
// make sure the SLPTR pin is low first
CHB_SLPTR_PORT &= ~(_BV(CHB_SLPTR_PIN));
// make the SLPTR pin an output
CHB_SLPTR_DDIR |= _BV(CHB_SLPTR_PIN);
// we need to allow some time for the PLL to lock
chb_delay_us(TIME_SLEEP_TO_TRX_OFF);
// Turn the transceiver back on
chb_set_state(RX_STATE);
}
}
U8 chb_tx(U8 *hdr, U8 *data, U8 len)
{
U8 state = chb_get_state();
pcb_t *pcb = chb_get_pcb();
if ((state == BUSY_TX) || (state == BUSY_TX_ARET))
{
return RADIO_WRONG_STATE;
}
// transition to the Transmit state
chb_set_state(TX_ARET_ON);
// write frame to buffer. first write header into buffer (add 1 for len byte), then data.
chb_frame_write(hdr, CHB_HDR_SZ + 1, data, len);
//Do frame transmission.
pcb->tx_busy = true;
chb_reg_read_mod_write(TRX_STATE, CMD_TX_START, 0x1F);
// wait for the transmission to end, signalled by the TRX END flag
while (!pcb->tx_end);
pcb->tx_end = false;
// check the status of the transmission
return chb_get_status();
}
U8 chb_tx(U8 *hdr, U8 *data, U8 len)
{
U8 state = chb_get_state();
pcb_t *pcb = chb_get_pcb();
if ((state == BUSY_TX) || (state == BUSY_TX_ARET))
{
return RADIO_WRONG_STATE;
}
// TODO: check why we need to transition to the off state before we go to tx_aret_on
chb_set_state(TRX_OFF);
chb_set_state(TX_ARET_ON);
// TODO: try and start the frame transmission by writing TX_START command instead of toggling
// sleep pin...i just feel like it's kind of weird...
// write frame to buffer. first write header into buffer (add 1 for len byte), then data.
chb_frame_write(hdr, CHB_HDR_SZ + 1, data, len);
// TEST - check data in buffer
//{
// U8 i, len, tmp[30];
//
// len = 1 + CHB_HDR_SZ + len;
// chb_sram_read(0, len, tmp);
// for (i=0; i<len; i++)
// {
// printf("%02X ", tmp[i]);
// }
// printf("\n");
// state = chb_get_state();
// printf("State = %02X.\n", state);
//}
//TEST
//Do frame transmission. Toggle the SLP_TR pin to initiate the frame transmission.
CHB_SLPTR_ENABLE();
CHB_SLPTR_DISABLE();
// wait for the transmission to end, signalled by the TRX END flag
while (!pcb->tx_end);
pcb->tx_end = false;
// check the status of the transmission
return chb_get_status();
}
void chb_sleep(U8 enb)
{
if (enb)
{
// first we need to go to TRX OFF state
chb_set_state(TRX_OFF);
// set the SLPTR pin
CHB_SLPTR_ENABLE();
}
else
{
// make sure the SLPTR pin is low first
CHB_SLPTR_DISABLE();
// we need to allow some time for the PLL to lock
chb_delay_us(TIME_SLEEP_TO_TRX_OFF);
// Turn the transceiver back on
chb_set_state(RX_STATE);
}
}
void chb_ISR_Handler (void)
{
U8 dummy, state, intp_src = 0;
chb_pcb_t *pcb = chb_get_pcb();
CHB_ENTER_CRIT();
/*Read Interrupt source.*/
CHB_SPI_ENABLE();
/*Send Register address and read register content.*/
dummy = chb_xfer_byte(IRQ_STATUS | CHB_SPI_CMD_RR);
intp_src = chb_xfer_byte(0);
CHB_SPI_DISABLE();
while (intp_src)
{
/*Handle the incomming interrupt. Prioritized.*/
if ((intp_src & CHB_IRQ_RX_START_MASK))
{
intp_src &= ~CHB_IRQ_RX_START_MASK;
}
else if (intp_src & CHB_IRQ_TRX_END_MASK)
{
state = chb_get_state();
if ((state == RX_ON) || (state == RX_AACK_ON) || (state == BUSY_RX_AACK))
{
// get the ed measurement
pcb->ed = chb_reg_read(PHY_ED_LEVEL);
// get the crc
pcb->crc = (chb_reg_read(PHY_RSSI) & (1<<7)) ? 1 : 0;
// if the crc is not valid, then do not read the frame and set the rx flag
if (pcb->crc)
{
// get the data
chb_frame_read();
pcb->rcvd_xfers++;
pcb->data_rcv = true;
}
}
else
{
pcb->tx_end = true;
}
intp_src &= ~CHB_IRQ_TRX_END_MASK;
while (chb_set_state(RX_STATE) != RADIO_SUCCESS);
}
else if (intp_src & CHB_IRQ_TRX_UR_MASK)
{
intp_src &= ~CHB_IRQ_TRX_UR_MASK;
pcb->underrun++;
}
else if (intp_src & CHB_IRQ_PLL_UNLOCK_MASK)
{
intp_src &= ~CHB_IRQ_PLL_UNLOCK_MASK;
}
else if (intp_src & CHB_IRQ_PLL_LOCK_MASK)
{
intp_src &= ~CHB_IRQ_PLL_LOCK_MASK;
}
else if (intp_src & CHB_IRQ_BAT_LOW_MASK)
{
intp_src &= ~CHB_IRQ_BAT_LOW_MASK;
pcb->battlow++;
}
else
{
}
}
CHB_LEAVE_CRIT();
}
static void chb_radio_init()
{
U8 ieee_addr[8];
// reset chip
chb_reset();
// disable intps while we config the radio
chb_reg_write(IRQ_MASK, 0);
// force transceiver off while we configure the intps
chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F);
// make sure the transceiver is in the off state before proceeding
while ((chb_reg_read(TRX_STATUS) & 0x1f) != TRX_OFF);
// set radio cfg parameters
// **note** uncomment if these will be set to something other than default
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS);
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS);
//chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS);
//chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0);
//chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS);
//chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES);
// set frame version that we'll accept
chb_reg_read_mod_write(CSMA_SEED_1, CHB_FRM_VER << CHB_FVN_POS, 3 << CHB_FVN_POS);
// set interrupt mask
// re-enable intps while we config the radio
chb_reg_write(IRQ_MASK, (1<<IRQ_RX_START) | (1<<IRQ_TRX_END));
#if (CFG_CHIBI_PROMISCUOUS == 0)
// set autocrc mode
chb_reg_read_mod_write(TRX_CTRL_1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS);
#endif
// set up default phy modulation, data rate and power (Ex. OQPSK, 100 kbps, 868 MHz, 3dBm)
chb_set_mode(CFG_CHIBI_MODE); // Defined in projectconfig.h
chb_set_pwr(CFG_CHIBI_POWER); // Defined in projectconfig.h
chb_set_channel(CFG_CHIBI_CHANNEL); // Defined in projectconfig.h
// set fsm state
// put trx in rx auto ack mode
chb_set_state(RX_STATE);
// set pan ID
chb_reg_write16(PAN_ID_0, CFG_CHIBI_PANID); // Defined in projectconfig.h
// set short addr
// NOTE: Possibly get this from EEPROM
chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr());
// set long addr
// NOTE: Possibly get this from EEPROM
chb_get_ieee_addr(ieee_addr);
chb_reg_write64(IEEE_ADDR_0, ieee_addr);
#if (CHB_CC1190_PRESENT)
// set high gain mode pin to output and init to zero
gpioSetDir (CHB_CC1190_HGM_PORT, CHB_CC1190_HGM_PIN, 1);
gpioSetPullup (&CHB_CC1190_HGM_IOCONREG, gpioPullupMode_Inactive);
gpioSetValue (CHB_CC1190_HGM_PORT, CHB_CC1190_HGM_PIN, 0);
// set external power amp on AT86RF212
chb_reg_read_mod_write(TRX_CTRL_1, 1<<CHB_PA_EXT_EN_POS, 1<<CHB_PA_EXT_EN_POS);
// set power to lowest level possible
chb_set_pwr(0xd); // set to -11 dBm
#endif
// set interrupt/gpio pin to input
gpioSetDir (CHB_EINTPORT, CHB_EINTPIN, 0);
// set internal resistor on EINT pin to inactive
gpioSetPullup (&CHB_EINTPIN_IOCONREG, gpioPullupMode_Inactive);
// configure pin for interrupt
gpioSetInterrupt (CHB_EINTPORT,
CHB_EINTPIN,
gpioInterruptSense_Edge, // Edge-sensitive
gpioInterruptEdge_Single, // Single edge
gpioInterruptEvent_ActiveHigh); // High triggers interrupt
// enable interrupt
gpioIntEnable (CHB_EINTPORT,
CHB_EINTPIN);
if (chb_get_state() != RX_STATE)
{
// ERROR occurred initializing the radio. Print out error message.
printf(chb_err_init);
}
}
static error_t chb_radio_init()
{
U8 ieee_addr[8];
// reset chip (this can fail if there is a HW or config problem)
error_t error = chb_reset();
if (error)
{
return error;
}
// disable intps while we config the radio
chb_reg_write(IRQ_MASK, 0);
// force transceiver off while we configure the intps
chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F);
// make sure the transceiver is in the off state before proceeding
while ((chb_reg_read(TRX_STATUS) & 0x1f) != TRX_OFF);
// set radio cfg parameters
// **note** uncomment if these will be set to something other than default
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS);
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS);
//chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS);
//chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0);
//chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS);
//chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES);
// set frame version that we'll accept
chb_reg_read_mod_write(CSMA_SEED_1, CHB_FRM_VER << CHB_FVN_POS, 3 << CHB_FVN_POS);
// set interrupt mask
// re-enable intps while we config the radio
chb_reg_write(IRQ_MASK, (1<<IRQ_RX_START) | (1<<IRQ_TRX_END));
#if (CFG_CHIBI_PROMISCUOUS == 0)
// set autocrc mode
chb_reg_read_mod_write(TRX_CTRL_1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS);
#endif
// set up default phy modulation, data rate and power (Ex. OQPSK, 100 kbps, 868 MHz, 3dBm)
chb_set_mode(CFG_CHIBI_MODE); // Defined in projectconfig.h
chb_set_pwr(CFG_CHIBI_POWER); // Defined in projectconfig.h
chb_set_channel(CFG_CHIBI_CHANNEL); // Defined in projectconfig.h
// set fsm state
// put trx in rx auto ack mode
chb_set_state(RX_STATE);
// set pan ID
chb_reg_write16(PAN_ID_0, CFG_CHIBI_PANID); // Defined in projectconfig.h
// set short addr
// NOTE: Possibly get this from EEPROM
chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr());
// set long addr
// NOTE: Possibly get this from EEPROM
chb_get_ieee_addr(ieee_addr);
chb_reg_write64(IEEE_ADDR_0, ieee_addr);
#if (CHB_CC1190_PRESENT)
// set high gain mode pin to output and init to zero
GPIOSetDir(CFG_CHIBI_CC1190_HGM_PORT, CFG_CHIBI_CC1190_HGM_PIN, 1);
GPIOSetBitValue(CFG_CHIBI_CC1190_HGM_PORT, CFG_CHIBI_CC1190_HGM_PIN, 0);
// set external power amp on AT86RF212
chb_reg_read_mod_write(TRX_CTRL_1, 1<<CHB_PA_EXT_EN_POS, 1<<CHB_PA_EXT_EN_POS);
// set power to lowest level possible
chb_set_pwr(0xd); // set to -11 dBm
#endif
// set interrupt/gpio pin to input
GPIOSetDir(CFG_CHIBI_EINTPORT, CFG_CHIBI_EINTPIN, 0);
// Channel 0, sense (0=edge, 1=level), polarity (0=low/falling, 1=high/rising)
GPIOSetPinInterrupt( 0, CFG_CHIBI_EINTPORT, CFG_CHIBI_EINTPIN, 0, 1 );
// Enable interrupt
// GPIOPinIntEnable( 0, 0 );
if (chb_get_state() != RX_STATE)
{
// ERROR occurred initializing the radio. Print out error message.
printf(chb_err_init);
return ERROR_DEVICENOTINITIALISED;
}
return ERROR_NONE;
}
static void chb_irq_handler()
{
U8 dummy, state, pinval;
pcb_t *pcb = chb_get_pcb();
// find out who issued the interrupt
intp_src |= chb_reg_read(IRQ_STATUS);
while (intp_src)
{
/*Handle the incomming interrupt. Prioritized.*/
if ((intp_src & CHB_IRQ_RX_START_MASK))
{
intp_src &= ~CHB_IRQ_RX_START_MASK;
}
else if (intp_src & CHB_IRQ_TRX_END_MASK)
{
state = chb_get_state();
if ((state == RX_ON) || (state == RX_AACK_ON) || (state == BUSY_RX_AACK))
{
// get the ed measurement
pcb->ed = chb_reg_read(PHY_ED_LEVEL);
// get the crc
pcb->crc = (chb_reg_read(PHY_RSSI) & (1<<7)) ? 1 : 0;
// if the crc is not valid, then do not read the frame and set the rx flag
// CHECK COMMENTED OUT FOR PROMISCOUS MODE OPERATION
//if (pcb->crc)
//{
pcb->data_rcv = true;
chb_frame_read(); // get the data
pcb->rcvd_xfers++;
//}
}
intp_src &= ~CHB_IRQ_TRX_END_MASK;
// THIS IS CHANGED FOR PROMISCOUS MODE (to match above mode setting change):
//while (chb_set_state(RX_AACK_ON) != RADIO_SUCCESS);
while (chb_set_state(RX_ON) != RADIO_SUCCESS);
}
else if (intp_src & CHB_IRQ_TRX_UR_MASK)
{
intp_src &= ~CHB_IRQ_TRX_UR_MASK;
pcb->underrun++;
}
else if (intp_src & CHB_IRQ_PLL_UNLOCK_MASK)
{
intp_src &= ~CHB_IRQ_PLL_UNLOCK_MASK;
}
else if (intp_src & CHB_IRQ_PLL_LOCK_MASK)
{
intp_src &= ~CHB_IRQ_PLL_LOCK_MASK;
}
else if (intp_src & CHB_IRQ_BAT_LOW_MASK)
{
intp_src &= ~CHB_IRQ_BAT_LOW_MASK;
pcb->battlow++;
}
else
{
}
}
rx_intp_flag = false;
CHB_IRQ_ENABLE();
}
static void chb_radio_init()
{
U8 ieee_addr[8];
U8 part_num;
// disable intps while we config the radio
chb_reg_write(IRQ_MASK, 0);
// force transceiver off while we configure the intps
chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F);
chb_delay_us(TIME_P_ON_TO_TRX_OFF);
// set radio cfg parameters
// **note** uncomment if these will be set to something other than default
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS);
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS);
//chb_reg_read_mod_write(CSMA_SEED_1, CHB_MIN_BE << CHB_MIN_BE_POS, 0x3 << CHB_MIN_BE_POS);
//chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS);
//chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0);
//chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS);
//chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES);
//chb_reg_read_mod_write(PHY_TX_PWR, CHB_TX_PWR, 0xf);
// identify device
part_num = chb_reg_read(PART_NUM);
switch (part_num)
{
case CHB_AT86RF230:
// set default channel
chb_set_channel(CHB_2_4GHZ_DEFAULT_CHANNEL);
#if (CHIBI_PROMISCUOUS == 0)
// set autocrc mode
chb_reg_read_mod_write(PHY_TX_PWR, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS);
#endif
break;
case CHB_AT86RF231:
// set default channel
chb_set_channel(CHB_2_4GHZ_DEFAULT_CHANNEL);
#if (CHIBI_PROMISCUOUS == 0)
// set autocrc mode
chb_reg_read_mod_write(PHY_TX_PWR, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS);
#endif
break;
case CHB_AT86RF212:
// set mode to OQPSK or BPSK depending on setting
chb_set_mode(CHB_INIT_MODE);
// set default channel and tx power to max
chb_set_channel(CHB_900MHZ_DEFAULT_CHANNEL);
chb_reg_read_mod_write(PHY_TX_PWR, CHB_900MHZ_TX_PWR, 0xf);
#if (CHIBI_PROMISCUOUS == 0)
// set autocrc mode
chb_reg_read_mod_write(TRX_CTRL1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS);
#endif
break;
default:
Serial.print("ERROR: Unknown radio detected.\n");
break;
}
// set transceiver's fsm state
chb_set_state(RX_STATE);
// set pan ID
chb_reg_write16(PAN_ID_0, CHB_PAN_ID);
// set short addr
// NOTE: Possibly get this from EEPROM
chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr());
// set long addr
// NOTE: Possibly get this from EEPROM
chb_get_ieee_addr(ieee_addr);
chb_reg_write64(IEEE_ADDR_0, ieee_addr);
// do a read of the interrupt register to clear the interrupt bits
chb_reg_read(IRQ_STATUS);
// re-enable intps while we config the radio
chb_reg_write(IRQ_MASK, 0x8);
// enable mcu intp pin on INT6 for rising edge
CFG_CHB_INTP();
if (chb_get_state() != RX_STATE)
{
// ERROR occurred initializing the radio. Print out error message.
char buf[50];
// grab the error message from flash & print it out
strcpy_P(buf, chb_err_init);
Serial.print(buf);
}
}
static void chb_radio_init()
{
U8 ieee_addr[8];
// reset chip
chb_reset();
// disable intps while we config the radio
chb_reg_write(IRQ_MASK, 0);
// force transceiver off while we configure the intps
chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F);
// make sure the transceiver is in the off state before proceeding
while ((chb_reg_read(TRX_STATUS) & 0x1f) != TRX_OFF);
// set radio cfg parameters
// **note** uncomment if these will be set to something other than default
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS);
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS);
//chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS);
//chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0);
//chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS);
//chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES);
// set frame version that we'll accept
chb_reg_read_mod_write(CSMA_SEED_1, CHB_FRM_VER << CHB_FVN_POS, 3 << CHB_FVN_POS);
// set interrupt mask
// re-enable intps while we config the radio
chb_reg_write(IRQ_MASK, (1<<IRQ_RX_START) | (1<<IRQ_TRX_END));
// set autocrc mode
chb_reg_read_mod_write(TRX_CTRL_1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS);
// set up default phy modulation and data rate - OQPSK, 250 kbps, 915 MHz
chb_set_mode(CHB_INIT_MODE);
chb_set_channel(CHB_CHANNEL);
// set fsm state
// put trx in rx auto ack mode
chb_set_state(RX_AACK_ON);
// set pan ID
chb_reg_write16(PAN_ID_0, CHB_PAN_ID);
// set short addr
// NOTE: Possibly get this from EEPROM
chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr());
// set long addr
// NOTE: Possibly get this from EEPROM
chb_get_ieee_addr(ieee_addr);
chb_reg_write64(IEEE_ADDR_0, ieee_addr);
// enable mcu intp pin on INT4
CFG_CHB_INTP_RISE_EDGE();
while (chb_get_state() != RX_AACK_ON);
}
static void chb_radio_init()
{
U8 ieee_addr[8];
// reset chip
chb_reset();
// disable intps while we config the radio
chb_reg_write(IRQ_MASK, 0);
// force transceiver off while we configure the intps
chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F);
// make sure the transceiver is in the off state before proceeding
while ((chb_reg_read(TRX_STATUS) & 0x1f) != CHB_TRX_OFF);
// set radio cfg parameters
// **note** uncomment if these will be set to something other than default
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS);
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS);
//chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS);
//chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0);
//chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS);
//chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES);
// set frame version that we'll accept
chb_reg_read_mod_write(CSMA_SEED_1, CHB_FRM_VER << CHB_FVN_POS, 3 << CHB_FVN_POS);
// set interrupt mask
// re-enable intps while we config the radio
chb_reg_write(IRQ_MASK, (1<<IRQ_RX_START) | (1<<IRQ_TRX_END));
#if (CHB_PROMISCUOUS == 0)
// set autocrc mode
chb_reg_read_mod_write(TRX_CTRL_1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS);
#endif
// set up default phy modulation and data rate - OQPSK, 250 kbps, 915 MHz
chb_set_mode(CHB_INIT_MODE);
chb_set_channel(CHB_CHANNEL);
// set fsm state
// put trx in rx auto ack mode
chb_set_state(RX_STATE);
// set pan ID
chb_reg_write16(PAN_ID_0, CHB_PAN_ID);
// set short addr
// NOTE: Possibly get this from EEPROM
chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr());
// set long addr
// NOTE: Possibly get this from EEPROM
chb_get_ieee_addr(ieee_addr);
chb_reg_write64(IEEE_ADDR_0, ieee_addr);
#if (CHB_CC1190_PRESENT)
// set high gain mode pin to output and init to zero
CHB_CC1190_HGM_DDIR |= 1<<CHB_CC1190_HGM_PIN;
CHB_CC1190_HGM_PORT &= ~(1<<CHB_CC1190_HGM_PIN);
// set external power amp on AT86RF212
chb_reg_read_mod_write(TRX_CTRL_1, 1<<CHB_PA_EXT_EN_POS, 1<<CHB_PA_EXT_EN_POS);
// set power to 0 dBm if CC1190 is being used.
chb_set_pwr(0x24);
#endif
// enable mcu intp pin
CFG_CHB_INTP_RISE_EDGE();
if (chb_get_state() != RX_STATE)
{
// ERROR occurred initializing the radio. Print out error message.
char buf[50];
// grab the error message from flash & print it out
strcpy_P(buf, chb_err_init);
printf(buf);
}
}
