/**
*! \brief Read the data for the generator
*! \param[in] delay_params_address The address of the delay extension
*! parameters
*! \param[in] params_address The address of the expander parameters
*! \return True if the expander finished correctly, False if there was an
*! error
*/
bool read_sdram_data(
address_t delay_params_address, address_t params_address) {
// Read the global parameters from the delay extension
uint32_t num_neurons = delay_params_address[N_ATOMS];
uint32_t neuron_bit_field_words = get_bit_field_size(num_neurons);
uint32_t n_stages = delay_params_address[N_DELAY_STAGES];
// Set up the bit fields
bit_field_t *neuron_delay_stage_config = (bit_field_t*) spin1_malloc(
n_stages * sizeof(bit_field_t));
for (uint32_t d = 0; d < n_stages; d++) {
neuron_delay_stage_config[d] = (bit_field_t)
&(delay_params_address[DELAY_BLOCKS])
+ (d * neuron_bit_field_words);
clear_bit_field(neuron_delay_stage_config[d], neuron_bit_field_words);
}
// Read the global parameters from the expander region
uint32_t n_out_edges = *params_address++;
uint32_t pre_slice_start = *params_address++;
uint32_t pre_slice_count = *params_address++;
log_debug("Generating %u delay edges for %u atoms starting at %u",
n_out_edges, pre_slice_count, pre_slice_start);
// Go through each connector and make the delay data
for (uint32_t edge = 0; edge < n_out_edges; edge++) {
if (!read_delay_builder_region(
¶ms_address, neuron_delay_stage_config,
pre_slice_start, pre_slice_count)) {
return false;
}
}
return true;
}
void reset_out_spikes (void) { clear_bit_field (out_spikes, out_spikes_size); }
static inline void _reset_spikes() {
spikes->n_buffers = 0;
for (uint32_t n = n_spike_buffers_allocated; n > 0; n--) {
clear_bit_field(_out_spikes(n - 1), n_spike_buffer_words);
}
}
//! \brief clears the currently recorded spikes
void out_spikes_reset() {
clear_bit_field(out_spikes, out_spikes_size);
}
