void disable_sead_irq(unsigned int irq_nr)
{
if (irq_nr == SEADINT_UART0)
clear_cp0_status(0x00000400);
else
if (irq_nr == SEADINT_UART1)
clear_cp0_status(0x00000800);
}
asmlinkage void __init
init_arch(int argc, char **argv, char **envp, int *prom_vec)
{
unsigned int s;
/* Determine which MIPS variant we are running on. */
cpu_probe();
prom_init(argc, argv, envp, prom_vec);
#ifdef CONFIG_SGI_IP22
sgi_sysinit();
#endif
cpu_report();
/*
* Determine the mmu/cache attached to this machine,
* then flush the tlb and caches. On the r4xx0
* variants this also sets CP0_WIRED to zero.
*/
loadmmu();
/* Disable coprocessors and set FPU for 16/32 FPR register model */
clear_cp0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
set_cp0_status(ST0_CU0);
start_kernel();
}
asmlinkage void __init init_arch(int argc, char **argv, char **envp,
int *prom_vec)
{
/* Determine which MIPS variant we are running on. */
cpu_probe();
prom_init(argc, argv, envp, prom_vec);
#ifdef CONFIG_SGI_IP22
sgi_sysinit();
#endif
cpu_report();
/*
* Determine the mmu/cache attached to this machine, then flush the
* tlb and caches. On the r4xx0 variants this also sets CP0_WIRED to
* zero.
*/
load_mmu();
/*
* On IP27, I am seeing the TS bit set when the kernel is loaded.
* Maybe because the kernel is in ckseg0 and not xkphys? Clear it
* anyway ...
*/
clear_cp0_status(ST0_BEV|ST0_TS|ST0_CU1|ST0_CU2|ST0_CU3);
set_cp0_status(ST0_CU0|ST0_KX|ST0_SX|ST0_FR);
start_kernel();
}
void
ddb5477_irq_setup(void)
{
db_run(printk("ddb5477_irq_setup invoked.\n"));
/* by default, we disable all interrupts and route all vrc5477
* interrupts to pin 0 (irq 2) */
ddb_out32(DDB_INTCTRL0, 0);
ddb_out32(DDB_INTCTRL1, 0);
ddb_out32(DDB_INTCTRL2, 0);
ddb_out32(DDB_INTCTRL3, 0);
clear_cp0_status(0xff00);
set_cp0_status(0x0400);
/* setup PCI interrupt attributes */
set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
/*
* for debugging purpose, we enable several error interrupts
* and route them to pin 1. (IP3)
*/
/* cpu parity check - 0 */
ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
/* cpu no-target decode - 1 */
ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
/* local bus read time-out - 7 */
ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
/* PCI SERR# - 14 */
ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
/* PCI internal error - 15 */
ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
/* IOPCI SERR# - 30 */
ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
/* IOPCI internal error - 31 */
ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
/* init all controllers */
mips_cpu_irq_init(0);
vrc5477_irq_init(8);
/* hook up the first-level interrupt handler */
set_except_vector(0, ddb5477_handle_int);
}
void prom_init_secondary(void)
{
/* Set up kseg0 to be cachable coherent */
clear_cp0_config(CONF_CM_CMASK);
set_cp0_config(0x5);
/* Enable interrupts for lines 0-4 */
clear_cp0_status(0xe000);
set_cp0_status(0x1f01);
}
void __init init_IRQ(void)
{
/* Invoke board-specific irq setup */
irq_setup();
#ifdef CONFIG_REMOTE_DEBUG
extern void breakpoint(void);
extern void set_debug_traps(void);
extern void rs_kgdb_hook(void);
rs_kgdb_hook();
clear_cp0_status(STATUSF_IP2);
clear_cp0_status(STATUSF_IP3);
clear_cp0_status(STATUSF_IP4);
clear_cp0_status(STATUSF_IP5);
clear_cp0_status(STATUSF_IP6);
clear_cp0_status(STATUSF_IP7);
printk("Wait for gdb client connection ...\n");
set_debug_traps();
set_cp0_status(STATUSF_IP2);
set_cp0_status(STATUSF_IP3);
set_cp0_status(STATUSF_IP4);
set_cp0_status(STATUSF_IP5);
set_cp0_status(STATUSF_IP6);
set_cp0_status(STATUSF_IP7);
breakpoint();
#endif
}
void __init brcm_irq_setup(void)
{
extern asmlinkage void brcmIRQ(void);
/* In 2.4.3 Kernel this was done in trap_init. In 2.4.17 it was
* moved to SMP code, which is only used by MIPS64. In other words
* Linux is free, you get what you pay for */
clear_cp0_status(ST0_BEV);
set_except_vector(0, brcmIRQ);
change_cp0_status(ST0_IM, ALLINTS_NOTIMER);
#ifdef CONFIG_REMOTE_DEBUG
rs_kgdb_hook(0);
#endif
}
void momenco_ocelot_restart(char *command)
{
*(volatile char *) 0xbc000000 = 0x0f;
/*
* Ouch, we're still alive ... This time we take the silver bullet ...
* ... and find that we leave the hardware in a state in which the
* kernel in the flush locks up somewhen during of after the PCI
* detection stuff.
*/
clear_cp0_status(ST0_BEV | ST0_ERL);
change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
}
void __init init_IRQ(void)
{
int i;
/*
* Mask out all interrupt
*/
clear_cp0_status(0x0000ff00);
/* Now safe to set the exception vector. */
set_except_vector(0, mipsIRQ);
init_generic_irq();
for (i = 0; i <= SEADINT_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].lock = SPIN_LOCK_UNLOCKED;
irq_desc[i].handler = &sead_irq_type;
}
}
static void
mips_cpu_irq_disable(unsigned int irq)
{
clear_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
}
static void disable_irq4(unsigned int irq)
{
clear_cp0_status(STATUSF_IP4);
}
static void disable_cpu_irq(unsigned int irq)
{
clear_cp0_status(STATUSF_IP7);
}
void __init it8172_setup(void)
{
unsigned short dsr;
char *argptr;
u32 it_ver;
unsigned long config;
argptr = prom_getcmdline();
#ifdef CONFIG_SERIAL_CONSOLE
if ((argptr = strstr(argptr, "console=")) == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " console=ttyS0,115200");
}
#endif
config = read_32bit_cp0_register(CP0_CONFIG);
printk("SysClock frequency multiplier: %d\n",
((config>>28)&0x7) + 2);
clear_cp0_status(ST0_FR);
rtc_ops = &it8172_rtc_ops;
board_time_init = it8172_time_init;
board_timer_setup = it8172_timer_setup;
rtc_get_time = it8172_rtc_get_time;
//rtc_set_time = it8172_rtc_set_time;
_machine_restart = it8172_restart;
_machine_halt = it8172_halt;
_machine_power_off = it8172_power_off;
/*
* IO/MEM resources.
*
* revisit this area.
*/
set_io_port_base(KSEG1);
ioport_resource.start = it8172_resources.pci_io.start;
ioport_resource.end = it8172_resources.pci_io.end;
#ifdef CONFIG_IT8172_REVC
iomem_resource.start = it8172_resources.pci_mem.start;
iomem_resource.end = it8172_resources.pci_mem.end;
#else
iomem_resource.start = it8172_resources.pci_mem0.start;
iomem_resource.end = it8172_resources.pci_mem3.end;
#endif
#ifdef CONFIG_BLK_DEV_INITRD
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
#endif
/*
* Pull enabled devices out of standby
*/
IT_IO_READ16(IT_PM_DSR, dsr);
#ifdef CONFIG_SOUND_IT8172
dsr &= ~IT_PM_DSR_ACSB;
#else
dsr |= IT_PM_DSR_ACSB;
#endif
#ifdef CONFIG_BLK_DEV_IT8172
dsr &= ~IT_PM_DSR_IDESB;
ide_ops = &std_ide_ops;
#else
dsr |= IT_PM_DSR_IDESB;
#endif
IT_IO_WRITE16(IT_PM_DSR, dsr);
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
InitLPCInterface();
#if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_SNSC_MPU210)
if (SearchIT8712()) {
printk("Found IT8712 Super IO\n");
// enable IT8712 serial port
LPCSetConfig(LDN_SERIAL1, 0x30, 0x01); /* enable */
LPCSetConfig(LDN_SERIAL1, 0x23, 0x01); /* clock selection */
#if defined(CONFIG_MIPS_SNSC_MPU210)
// enable IT8712 serial port
LPCSetConfig(LDN_SERIAL2, 0x30, 0x01); /* enable */
LPCSetConfig(LDN_SERIAL2, 0x23, 0x01); /* clock selection */
#endif // defined(CONFIG_MIPS_SNSC_MPU210)
#ifdef CONFIG_PC_KEYB
if (init_8712_keyboard()) {
printk("Unable to initialize keyboard\n");
LPCSetConfig(LDN_KEYBOARD, 0x30, 0x0); /* disable keyboard */
}
else {
LPCSetConfig(LDN_KEYBOARD, 0x30, 0x1); /* enable keyboard */
LPCSetConfig(LDN_KEYBOARD, 0xf0, 0x2);
LPCSetConfig(LDN_KEYBOARD, 0x71, 0x3);
LPCSetConfig(LDN_MOUSE, 0x30, 0x1); /* enable mouse */
LPCSetConfig(0x4, 0x30, 0x1);
LPCSetConfig(0x4, 0xf4, LPCGetConfig(0x4, 0xf4) | 0x80);
if ((LPCGetConfig(LDN_KEYBOARD, 0x30) == 0) ||
(LPCGetConfig(LDN_MOUSE, 0x30) == 0))
printk("Error: keyboard or mouse not enabled\n");
kbd_ops = &std_kbd_ops;
}
#endif
}
else {
printk("IT8712 Super IO not found\n");
}
#endif
#ifdef CONFIG_IT8172_CIR
{
unsigned long data;
//printk("Enabling CIR0\n");
IT_IO_READ16(IT_PM_DSR, data);
data &= ~IT_PM_DSR_CIR0SB;
IT_IO_WRITE16(IT_PM_DSR, data);
//printk("DSR register: %x\n", (unsigned)IT_IO_READ16(IT_PM_DSR, data));
}
#endif
#ifdef CONFIG_IT8172_SCR0
{
unsigned i;
/* Enable Smart Card Reader 0 */
/* First power it up */
IT_IO_READ16(IT_PM_DSR, i);
i &= ~IT_PM_DSR_SCR0SB;
IT_IO_WRITE16(IT_PM_DSR, i);
/* Then initialize its registers */
outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
|IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
|IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
|IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
|IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SFR);
outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SCDR);
}
#endif /* CONFIG_IT8172_SCR0 */
#ifdef CONFIG_IT8172_SCR1
{
unsigned i;
/* Enable Smart Card Reader 1 */
/* First power it up */
IT_IO_READ16(IT_PM_DSR, i);
i &= ~IT_PM_DSR_SCR1SB;
IT_IO_WRITE16(IT_PM_DSR, i);
/* Then initialize its registers */
outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
|IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
|IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
|IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
|IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SFR);
outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SCDR);
}
#endif /* CONFIG_IT8172_SCR1 */
}
