static void __init rk3188_common_clk_init(struct device_node *np)
{
void __iomem *reg_base;
struct clk *clk;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
/* Fixed-clock should be registered before all others */
clk=clk_fixed("xin24m",24000000);
if (IS_ERR(clk))
pr_warn("%s: could not register clock xin24m: %ld\n",
__func__, PTR_ERR(clk));
/* xin12m is created by an cru-internal divider */
clk = clk_fixed_factor("xin12m", "xin24m", 1, 2, 0);
if (IS_ERR(clk))
pr_warn("%s: could not register clock xin12m: %ld\n",
__func__, PTR_ERR(clk));
clk = clk_fixed_factor("usb480m", "xin24m", 20, 1, 0);
if (IS_ERR(clk))
pr_warn("%s: could not register clock usb480m: %ld\n",
__func__, PTR_ERR(clk));
rockchip_clk_register_branches(common_clk_branches,
ARRAY_SIZE(common_clk_branches));
rockchip_clk_protect_critical(rk3188_critical_clocks,
ARRAY_SIZE(rk3188_critical_clocks));
}
int mvebu_coreclk_probe(struct device_d *dev)
{
struct device_node *np = dev->device_node;
const struct of_device_id *match;
const struct coreclk_soc_desc *desc;
const char *tclk_name = "tclk";
const char *cpuclk_name = "cpuclk";
void __iomem *base;
unsigned long rate;
int n;
match = of_match_node(mvebu_coreclk_ids, np);
if (!match)
return -EINVAL;
desc = (const struct coreclk_soc_desc *)match->data;
/* Get SAR base address */
base = dev_request_mem_region(dev, 0);
if (!base)
return -EINVAL;
/* Allocate struct for TCLK, cpu clk, and core ratio clocks */
clk_data.clk_num = 2 + desc->num_ratios;
clk_data.clks = xzalloc(clk_data.clk_num * sizeof(struct clk *));
/* Register TCLK */
of_property_read_string_index(np, "clock-output-names", 0,
&tclk_name);
rate = desc->get_tclk_freq(base);
clk_data.clks[0] = clk_fixed(tclk_name, rate);
WARN_ON(IS_ERR(clk_data.clks[0]));
/* Register CPU clock */
of_property_read_string_index(np, "clock-output-names", 1,
&cpuclk_name);
rate = desc->get_cpu_freq(base);
clk_data.clks[1] = clk_fixed(cpuclk_name, rate);
WARN_ON(IS_ERR(clk_data.clks[1]));
/* Register fixed-factor clocks derived from CPU clock */
for (n = 0; n < desc->num_ratios; n++) {
const char *rclk_name = desc->ratios[n].name;
int mult, div;
of_property_read_string_index(np, "clock-output-names",
2+n, &rclk_name);
desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
clk_data.clks[2+n] = clk_fixed_factor(rclk_name, cpuclk_name,
mult, div, 0);
WARN_ON(IS_ERR(clk_data.clks[2+n]));
};
return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
