Esempio n. 1
0
void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
		       u32 clkrst5_base, u32 clkrst6_base)
{
	struct prcmu_fw_version *fw_version;
	struct device_node *np = NULL;
	struct device_node *child = NULL;
	const char *sgaclk_parent = NULL;
	struct clk *clk, *rtc_clk, *twd_clk;

	if (of_have_populated_dt())
		np = of_find_matching_node(NULL, u8500_clk_of_match);
	if (!np) {
		pr_err("Either DT or U8500 Clock node not found\n");
		return;
	}

	/* Clock sources */
	clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	prcmu_clk[PRCMU_PLLSOC0] = clk;

	clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	prcmu_clk[PRCMU_PLLSOC1] = clk;

	clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	prcmu_clk[PRCMU_PLLDDR] = clk;

	/* FIXME: Add sys, ulp and int clocks here. */

	rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
				CLK_IS_ROOT|CLK_IGNORE_UNUSED,
				32768);

	/* PRCMU clocks */
	fw_version = prcmu_get_fw_version();
	if (fw_version != NULL) {
		switch (fw_version->project) {
		case PRCMU_FW_PROJECT_U8500_C2:
		case PRCMU_FW_PROJECT_U8520:
		case PRCMU_FW_PROJECT_U8420:
			sgaclk_parent = "soc0_pll";
			break;
		default:
			break;
		}
	}

	if (sgaclk_parent)
		clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
					PRCMU_SGACLK, 0);
	else
		clk = clk_reg_prcmu_gate("sgclk", NULL,
					PRCMU_SGACLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_SGACLK] = clk;

	clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_UARTCLK] = clk;

	clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_MSP02CLK] = clk;

	clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_MSP1CLK] = clk;

	clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_I2CCLK] = clk;

	clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_SLIMCLK] = clk;

	clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_PER1CLK] = clk;

	clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_PER2CLK] = clk;

	clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_PER3CLK] = clk;

	clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_PER5CLK] = clk;

	clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_PER6CLK] = clk;

	clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_PER7CLK] = clk;

	clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_LCDCLK] = clk;

	clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_BMLCLK] = clk;

	clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_HSITXCLK] = clk;

	clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_HSIRXCLK] = clk;

	clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_HDMICLK] = clk;

	clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_APEATCLK] = clk;

	clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_APETRACECLK] = clk;

	clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_MCDECLK] = clk;

	clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
				CLK_IS_ROOT);
	prcmu_clk[PRCMU_IPI2CCLK] = clk;

	clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
				CLK_IS_ROOT);
	prcmu_clk[PRCMU_DSIALTCLK] = clk;

	clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_DMACLK] = clk;

	clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_B2R2CLK] = clk;

	clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_TVCLK] = clk;

	clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_SSPCLK] = clk;

	clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_RNGCLK] = clk;

	clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_UICCCLK] = clk;

	clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
	prcmu_clk[PRCMU_TIMCLK] = clk;

	clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
					100000000,
					CLK_IS_ROOT|CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_SDMMCCLK] = clk;

	clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_PLLDSI] = clk;

	clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_DSI0CLK] = clk;

	clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_DSI1CLK] = clk;

	clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_DSI0ESCCLK] = clk;

	clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_DSI1ESCCLK] = clk;

	clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
	prcmu_clk[PRCMU_DSI2ESCCLK] = clk;

	clk = clk_reg_prcmu_scalable_rate("armss", NULL,
				PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	prcmu_clk[PRCMU_ARMSS] = clk;

	twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
				CLK_IGNORE_UNUSED, 1, 2);

	/*
	 * FIXME: Add special handled PRCMU clocks here:
	 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
	 * 2. ab9540_clkout1yuv, see clkout0yuv
	 */

	/* PRCC P-clocks */
	clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
				BIT(0), 0);
	PRCC_PCLK_STORE(clk, 1, 0);

	clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
				BIT(1), 0);
	PRCC_PCLK_STORE(clk, 1, 1);

	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
				BIT(2), 0);
	PRCC_PCLK_STORE(clk, 1, 2);

	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
				BIT(3), 0);
	PRCC_PCLK_STORE(clk, 1, 3);

	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
				BIT(4), 0);
	PRCC_PCLK_STORE(clk, 1, 4);

	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
				BIT(5), 0);
	PRCC_PCLK_STORE(clk, 1, 5);

	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
				BIT(6), 0);
	PRCC_PCLK_STORE(clk, 1, 6);

	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
				BIT(7), 0);
	PRCC_PCLK_STORE(clk, 1, 7);

	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
				BIT(8), 0);
	PRCC_PCLK_STORE(clk, 1, 8);

	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
				BIT(9), 0);
	PRCC_PCLK_STORE(clk, 1, 9);

	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
				BIT(10), 0);
	PRCC_PCLK_STORE(clk, 1, 10);

	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
				BIT(11), 0);
	PRCC_PCLK_STORE(clk, 1, 11);

	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
				BIT(0), 0);
	PRCC_PCLK_STORE(clk, 2, 0);

	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
				BIT(1), 0);
	PRCC_PCLK_STORE(clk, 2, 1);

	clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
				BIT(2), 0);
	PRCC_PCLK_STORE(clk, 2, 2);

	clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
				BIT(3), 0);
	PRCC_PCLK_STORE(clk, 2, 3);

	clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
				BIT(4), 0);
	PRCC_PCLK_STORE(clk, 2, 4);

	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
				BIT(5), 0);
	PRCC_PCLK_STORE(clk, 2, 5);

	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
				BIT(6), 0);
	PRCC_PCLK_STORE(clk, 2, 6);

	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
				BIT(7), 0);
	PRCC_PCLK_STORE(clk, 2, 7);

	clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
				BIT(8), 0);
	PRCC_PCLK_STORE(clk, 2, 8);

	clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
				BIT(9), 0);
	PRCC_PCLK_STORE(clk, 2, 9);

	clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
				BIT(10), 0);
	PRCC_PCLK_STORE(clk, 2, 10);

	clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
				BIT(11), 0);
	PRCC_PCLK_STORE(clk, 2, 11);

	clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
				BIT(12), 0);
	PRCC_PCLK_STORE(clk, 2, 12);

	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
				BIT(0), 0);
	PRCC_PCLK_STORE(clk, 3, 0);

	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
				BIT(1), 0);
	PRCC_PCLK_STORE(clk, 3, 1);

	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
				BIT(2), 0);
	PRCC_PCLK_STORE(clk, 3, 2);

	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
				BIT(3), 0);
	PRCC_PCLK_STORE(clk, 3, 3);

	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
				BIT(4), 0);
	PRCC_PCLK_STORE(clk, 3, 4);

	clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
				BIT(5), 0);
	PRCC_PCLK_STORE(clk, 3, 5);

	clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
				BIT(6), 0);
	PRCC_PCLK_STORE(clk, 3, 6);

	clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
				BIT(7), 0);
	PRCC_PCLK_STORE(clk, 3, 7);

	clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
				BIT(8), 0);
	PRCC_PCLK_STORE(clk, 3, 8);

	clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
				BIT(0), 0);
	PRCC_PCLK_STORE(clk, 5, 0);

	clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
				BIT(1), 0);
	PRCC_PCLK_STORE(clk, 5, 1);

	clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
				BIT(0), 0);
	PRCC_PCLK_STORE(clk, 6, 0);

	clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
				BIT(1), 0);
	PRCC_PCLK_STORE(clk, 6, 1);

	clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
				BIT(2), 0);
	PRCC_PCLK_STORE(clk, 6, 2);

	clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
				BIT(3), 0);
	PRCC_PCLK_STORE(clk, 6, 3);

	clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
				BIT(4), 0);
	PRCC_PCLK_STORE(clk, 6, 4);

	clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
				BIT(5), 0);
	PRCC_PCLK_STORE(clk, 6, 5);

	clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
				BIT(6), 0);
	PRCC_PCLK_STORE(clk, 6, 6);

	clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
				BIT(7), 0);
	PRCC_PCLK_STORE(clk, 6, 7);

	/* PRCC K-clocks
	 *
	 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
	 * by enabling just the K-clock, even if it is not a valid parent to
	 * the K-clock. Until drivers get fixed we might need some kind of
	 * "parent muxed join".
	 */

	/* Periph1 */
	clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
			clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 1, 0);

	clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
			clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 1, 1);

	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
			clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 1, 2);

	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
			clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 1, 3);

	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
			clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 1, 4);

	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
			clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 1, 5);

	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
			clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 1, 6);

	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
			clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 1, 8);

	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
			clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 1, 9);

	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
			clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 1, 10);

	/* Periph2 */
	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
			clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 2, 0);

	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
			clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 2, 2);

	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
			clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 2, 3);

	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
			clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 2, 4);

	clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
			clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 2, 5);

	/* Note that rate is received from parent. */
	clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
			clkrst2_base, BIT(6),
			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
	PRCC_KCLK_STORE(clk, 2, 6);

	clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
			clkrst2_base, BIT(7),
			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
	PRCC_KCLK_STORE(clk, 2, 7);

	/* Periph3 */
	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
			clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 3, 1);

	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
			clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 3, 2);

	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
			clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 3, 3);

	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
			clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 3, 4);

	clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
			clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 3, 5);

	clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
			clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 3, 6);

	clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
			clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 3, 7);

	/* Periph6 */
	clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
			clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
	PRCC_KCLK_STORE(clk, 6, 0);

	for_each_child_of_node(np, child) {
		static struct clk_onecell_data clk_data;

		if (!of_node_cmp(child->name, "prcmu-clock")) {
			clk_data.clks = prcmu_clk;
			clk_data.clk_num = ARRAY_SIZE(prcmu_clk);
			of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data);
		}
		if (!of_node_cmp(child->name, "prcc-periph-clock"))
			of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);

		if (!of_node_cmp(child->name, "prcc-kernel-clock"))
			of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);

		if (!of_node_cmp(child->name, "rtc32k-clock"))
			of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk);

		if (!of_node_cmp(child->name, "smp-twd-clock"))
			of_clk_add_provider(child, of_clk_src_simple_get, twd_clk);
	}
}
Esempio n. 2
0
void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
		    u32 clkrst5_base, u32 clkrst6_base)
{
	struct prcmu_fw_version *fw_version;
	const char *sgaclk_parent = NULL;
	struct clk *clk;

	/* Clock sources */
	clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	clk_register_clkdev(clk, "soc0_pll", NULL);

	clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	clk_register_clkdev(clk, "soc1_pll", NULL);

	clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	clk_register_clkdev(clk, "ddr_pll", NULL);

	/* FIXME: Add sys, ulp and int clocks here. */

	clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
				CLK_IS_ROOT|CLK_IGNORE_UNUSED,
				32768);
	clk_register_clkdev(clk, "clk32k", NULL);
	clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");

	/* PRCMU clocks */
	fw_version = prcmu_get_fw_version();
	if (fw_version != NULL) {
		switch (fw_version->project) {
		case PRCMU_FW_PROJECT_U8500_C2:
		case PRCMU_FW_PROJECT_U8520:
		case PRCMU_FW_PROJECT_U8420:
			sgaclk_parent = "soc0_pll";
			break;
		default:
			break;
		}
	}

	if (sgaclk_parent)
		clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
					PRCMU_SGACLK, 0);
	else
		clk = clk_reg_prcmu_gate("sgclk", NULL,
					PRCMU_SGACLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "mali");

	clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "UART");

	clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "MSP02");

	clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "MSP1");

	clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "I2C");

	clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "slim");

	clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH1");

	clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH2");

	clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH3");

	clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH5");

	clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH6");

	clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH7");

	clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "lcd");
	clk_register_clkdev(clk, "lcd", "mcde");

	clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "bml");

	clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);

	clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);

	clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "hdmi");
	clk_register_clkdev(clk, "hdmi", "mcde");

	clk = clk_reg_prcmu_scalable("apeatclk", NULL, PRCMU_APEATCLK, 0,
				     CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "apeat");

	clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "apetrace");

	clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "mcde");
	clk_register_clkdev(clk, "mcde", "mcde");
	clk_register_clkdev(clk, "dsisys", "dsilink.0");
	clk_register_clkdev(clk, "dsisys", "dsilink.1");
	clk_register_clkdev(clk, "dsisys", "dsilink.2");

	clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
				CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "ipi2");

	clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
				CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "dsialt");

	clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "dma40.0");

	clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "b2r2");
	clk_register_clkdev(clk, NULL, "b2r2_core");
	clk_register_clkdev(clk, NULL, "U8500-B2R2.0");

	clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "tv");
	clk_register_clkdev(clk, "tv", "mcde");

	clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "SSP");

	clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "rngclk");

	clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "uicc");

	clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "mtu0");
	clk_register_clkdev(clk, NULL, "mtu1");

	clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
					100000000,
					CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdmmc");

	clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsihs2", "mcde");
	clk_register_clkdev(clk, "dsihs2", "dsilink.2");


	clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsihs0", "mcde");
	clk_register_clkdev(clk, "dsihs0", "dsilink.0");

	clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsihs1", "mcde");
	clk_register_clkdev(clk, "dsihs1", "dsilink.1");

	clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsilp0", "dsilink.0");
	clk_register_clkdev(clk, "dsilp0", "mcde");

	clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsilp1", "dsilink.1");
	clk_register_clkdev(clk, "dsilp1", "mcde");

	clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsilp2", "dsilink.2");
	clk_register_clkdev(clk, "dsilp2", "mcde");

	clk = clk_reg_prcmu_scalable_rate("armss", NULL,
				PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	clk_register_clkdev(clk, "armss", NULL);

	clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
				CLK_IGNORE_UNUSED, 1, 2);
	clk_register_clkdev(clk, NULL, "smp_twd");

	/*
	 * FIXME: Add special handled PRCMU clocks here:
	 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
	 * 2. ab9540_clkout1yuv, see clkout0yuv
	 */

	/* PRCC P-clocks */
	clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
				BIT(0), 0);
	clk_register_clkdev(clk, "apb_pclk", "uart0");

	clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
				BIT(1), 0);
	clk_register_clkdev(clk, "apb_pclk", "uart1");

	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
				BIT(2), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");

	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
				BIT(3), 0);
	clk_register_clkdev(clk, "apb_pclk", "msp0");
	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0");

	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
				BIT(4), 0);
	clk_register_clkdev(clk, "apb_pclk", "msp1");
	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1");

	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
				BIT(5), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi0");

	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
				BIT(6), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");

	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
				BIT(7), 0);
	clk_register_clkdev(clk, NULL, "spi3");

	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
				BIT(8), 0);
	clk_register_clkdev(clk, "apb_pclk", "slimbus0");

	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
				BIT(9), 0);
	clk_register_clkdev(clk, NULL, "gpio.0");
	clk_register_clkdev(clk, NULL, "gpio.1");
	clk_register_clkdev(clk, NULL, "gpioblock0");

	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
				BIT(10), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");

	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
				BIT(11), 0);
	clk_register_clkdev(clk, "apb_pclk", "msp3");
	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3");

	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
				BIT(0), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");

	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
				BIT(1), 0);
	clk_register_clkdev(clk, NULL, "spi2");

	clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
				BIT(2), 0);
	clk_register_clkdev(clk, NULL, "spi1");

	clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
				BIT(3), 0);
	clk_register_clkdev(clk, NULL, "pwl");

	clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
				BIT(4), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi4");

	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
				BIT(5), 0);
	clk_register_clkdev(clk, "apb_pclk", "msp2");
	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2");

	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
				BIT(6), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi1");

	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
				BIT(7), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi3");

	clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
				BIT(8), 0);
	clk_register_clkdev(clk, NULL, "spi0");

	clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
				BIT(9), 0);
	clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");

	clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
				BIT(10), 0);
	clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");

	clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
				BIT(11), 0);
	clk_register_clkdev(clk, NULL, "gpio.6");
	clk_register_clkdev(clk, NULL, "gpio.7");
	clk_register_clkdev(clk, NULL, "gpioblock1");

	clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
				BIT(12), 0);

	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
				BIT(0), 0);
	clk_register_clkdev(clk, "fsmc", NULL);
	clk_register_clkdev(clk, NULL, "smsc911x.0");

	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
				BIT(1), 0);
	clk_register_clkdev(clk, "apb_pclk", "ssp0");

	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
				BIT(2), 0);
	clk_register_clkdev(clk, "apb_pclk", "ssp1");

	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
				BIT(3), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");

	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
				BIT(4), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi2");

	clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
				BIT(5), 0);
	clk_register_clkdev(clk, "apb_pclk", "ske");
	clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");

	clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
				BIT(6), 0);
	clk_register_clkdev(clk, "apb_pclk", "uart2");

	clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
				BIT(7), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi5");

	clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
				BIT(8), 0);
	clk_register_clkdev(clk, NULL, "gpio.2");
	clk_register_clkdev(clk, NULL, "gpio.3");
	clk_register_clkdev(clk, NULL, "gpio.4");
	clk_register_clkdev(clk, NULL, "gpio.5");
	clk_register_clkdev(clk, NULL, "gpioblock2");

	clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
				BIT(0), 0);
	clk_register_clkdev(clk, "usb", "musb-ux500.0");

	clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
				BIT(1), 0);
	clk_register_clkdev(clk, NULL, "gpio.8");
	clk_register_clkdev(clk, NULL, "gpioblock3");

	clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
				BIT(0), 0);
	clk_register_clkdev(clk, "apb_pclk", "rng");

	clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
				BIT(1), 0);
	clk_register_clkdev(clk, NULL, "cryp0");
	clk_register_clkdev(clk, NULL, "cryp1");

	clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
				BIT(2), 0);
	clk_register_clkdev(clk, NULL, "hash0");

	clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
				BIT(3), 0);
	clk_register_clkdev(clk, NULL, "pka");

	clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
				BIT(4), 0);
	clk_register_clkdev(clk, NULL, "hash1");

	clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
				BIT(5), 0);
	clk_register_clkdev(clk, NULL, "cfgreg");

	clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
				BIT(6), 0);
	clk_register_clkdev(clk, "apb_pclk", "mtu0");

	clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
				BIT(7), 0);
	clk_register_clkdev(clk, "apb_pclk", "mtu1");

	/* PRCC K-clocks
	 *
	 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
	 * by enabling just the K-clock, even if it is not a valid parent to
	 * the K-clock. Until drivers get fixed we might need some kind of
	 * "parent muxed join".
	 */

	/* Periph1 */
	clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
			clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "uart0");

	clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
			clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "uart1");

	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
			clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.1");

	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
			clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "msp0");
	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0");

	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
			clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "msp1");
	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1");

	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
			clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi0");

	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
			clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.2");

	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
			clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "slimbus0");

	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
			clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.4");

	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
			clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "msp3");
	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3");

	/* Periph2 */
	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
			clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.3");

	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
			clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi4");

	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
			clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "msp2");
	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2");

	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
			clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi1");

	clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
			clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi3");

	/* Note that rate is received from parent. */
	clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
			clkrst2_base, BIT(6),
			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
	clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
			clkrst2_base, BIT(7),
			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);

	/* Periph3 */
	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
			clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "ssp0");

	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
			clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "ssp1");

	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
			clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.0");

	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
			clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi2");

	clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
			clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "ske");
	clk_register_clkdev(clk, NULL, "nmk-ske-keypad");

	clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
			clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "uart2");

	clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
			clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi5");

	/* Periph6 */
	clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
			clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "rng");
}
Esempio n. 3
0
void u8540_clk_init(void)
{
	struct clk *clk;
	struct device_node *np = NULL;
	u32 bases[CLKRST_MAX];
	int i;

	if (of_have_populated_dt())
		np = of_find_matching_node(NULL, u8540_clk_of_match);
	if (!np) {
		pr_err("Either DT or U8540 Clock node not found\n");
		return;
	}
	for (i = 0; i < ARRAY_SIZE(bases); i++) {
		struct resource r;

		if (of_address_to_resource(np, i, &r))
			/* Not much choice but to continue */
			pr_err("failed to get CLKRST %d base address\n",
			       i + 1);
		bases[i] = r.start;
	}

	/* Clock sources. */
	/* Fixed ClockGen */
	clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	clk_register_clkdev(clk, "soc0_pll", NULL);

	clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	clk_register_clkdev(clk, "soc1_pll", NULL);

	clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	clk_register_clkdev(clk, "ddr_pll", NULL);

	clk = clk_register_fixed_rate(NULL, "rtc32k", NULL,
				CLK_IS_ROOT|CLK_IGNORE_UNUSED,
				32768);
	clk_register_clkdev(clk, "clk32k", NULL);
	clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");

	clk = clk_register_fixed_rate(NULL, "ulp38m4", NULL,
				CLK_IS_ROOT|CLK_IGNORE_UNUSED,
				38400000);

	clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "UART");

	/* msp02clk needs a abx500 clk as parent. Handle by abx500 clk driver */
	clk = clk_reg_prcmu_gate("msp02clk", "ab9540_sysclk12_b1",
			PRCMU_MSP02CLK, 0);
	clk_register_clkdev(clk, NULL, "MSP02");

	clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "MSP1");

	clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "I2C");

	clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "slim");

	clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH1");

	clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH2");

	clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH3");

	clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH5");

	clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH6");

	clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "PERIPH7");

	clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "lcd");
	clk_register_clkdev(clk, "lcd", "mcde");

	clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK,
				CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "bml");

	clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);

	clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);

	clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "hdmi");
	clk_register_clkdev(clk, "hdmi", "mcde");

	clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "apeat");

	clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
				CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "apetrace");

	clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "mcde");
	clk_register_clkdev(clk, "mcde", "mcde");
	clk_register_clkdev(clk, NULL, "dsilink.0");
	clk_register_clkdev(clk, NULL, "dsilink.1");
	clk_register_clkdev(clk, NULL, "dsilink.2");

	clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
				CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "ipi2");

	clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
				CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "dsialt");

	clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "dma40.0");

	clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "b2r2");
	clk_register_clkdev(clk, NULL, "b2r2_core");
	clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
	clk_register_clkdev(clk, NULL, "b2r2_1_core");

	clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "tv");
	clk_register_clkdev(clk, "tv", "mcde");

	clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "SSP");

	clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "rngclk");

	clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "uicc");

	clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "mtu0");
	clk_register_clkdev(clk, NULL, "mtu1");

	clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL,
					PRCMU_SDMMCCLK, 100000000,
					CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdmmc");

	clk = clk_reg_prcmu_opp_volt_scalable("sdmmchclk", NULL,
					PRCMU_SDMMCHCLK, 400000000,
					CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdmmchclk");

	clk = clk_reg_prcmu_gate("hvaclk", NULL, PRCMU_HVACLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "hva");

	clk = clk_reg_prcmu_gate("g1clk", NULL, PRCMU_G1CLK, CLK_IS_ROOT);
	clk_register_clkdev(clk, NULL, "g1");

	clk = clk_reg_prcmu_scalable("spare1clk", NULL, PRCMU_SPARE1CLK, 0,
				CLK_IS_ROOT|CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsilcd", "mcde");

	clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsihs2", "mcde");
	clk_register_clkdev(clk, "hs_clk", "dsilink.2");

	clk = clk_reg_prcmu_scalable("dsilcd_pll", "spare1clk",
				PRCMU_PLLDSI_LCD, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsilcd_pll", "mcde");

	clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsihs0", "mcde");

	clk = clk_reg_prcmu_scalable("dsi0lcdclk", "dsilcd_pll",
				PRCMU_DSI0CLK_LCD, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsihs0", "mcde");
	clk_register_clkdev(clk, "hs_clk", "dsilink.0");

	clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsihs1", "mcde");

	clk = clk_reg_prcmu_scalable("dsi1lcdclk", "dsilcd_pll",
				PRCMU_DSI1CLK_LCD, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "dsihs1", "mcde");
	clk_register_clkdev(clk, "hs_clk", "dsilink.1");

	clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "lp_clk", "dsilink.0");
	clk_register_clkdev(clk, "dsilp0", "mcde");

	clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "lp_clk", "dsilink.1");
	clk_register_clkdev(clk, "dsilp1", "mcde");

	clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, "lp_clk", "dsilink.2");
	clk_register_clkdev(clk, "dsilp2", "mcde");

	clk = clk_reg_prcmu_scalable_rate("armss", NULL,
				PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
	clk_register_clkdev(clk, "armss", NULL);

	clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
				CLK_IGNORE_UNUSED, 1, 2);
	clk_register_clkdev(clk, NULL, "smp_twd");

	/* PRCC P-clocks */
	/* Peripheral 1 : PRCC P-clocks */
	clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
				BIT(0), 0);
	clk_register_clkdev(clk, "apb_pclk", "uart0");

	clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
				BIT(1), 0);
	clk_register_clkdev(clk, "apb_pclk", "uart1");

	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
				BIT(2), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");

	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
				BIT(3), 0);
	clk_register_clkdev(clk, "apb_pclk", "msp0");
	clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.0");

	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
				BIT(4), 0);
	clk_register_clkdev(clk, "apb_pclk", "msp1");
	clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.1");

	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
				BIT(5), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi0");

	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
				BIT(6), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");

	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
				BIT(7), 0);
	clk_register_clkdev(clk, NULL, "spi3");

	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
				BIT(8), 0);
	clk_register_clkdev(clk, "apb_pclk", "slimbus0");

	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
				BIT(9), 0);
	clk_register_clkdev(clk, NULL, "gpio.0");
	clk_register_clkdev(clk, NULL, "gpio.1");
	clk_register_clkdev(clk, NULL, "gpioblock0");
	clk_register_clkdev(clk, "apb_pclk", "ab85xx-codec.0");

	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
				BIT(10), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");

	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
				BIT(11), 0);
	clk_register_clkdev(clk, "apb_pclk", "msp3");
	clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.3");

	/* Peripheral 2 : PRCC P-clocks */
	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
				BIT(0), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");

	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
				BIT(1), 0);
	clk_register_clkdev(clk, NULL, "spi2");

	clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
				BIT(2), 0);
	clk_register_clkdev(clk, NULL, "spi1");

	clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
				BIT(3), 0);
	clk_register_clkdev(clk, NULL, "pwl");

	clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
				BIT(4), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi4");

	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
				BIT(5), 0);
	clk_register_clkdev(clk, "apb_pclk", "msp2");
	clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.2");

	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
				BIT(6), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi1");

	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
				BIT(7), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi3");

	clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
				BIT(8), 0);
	clk_register_clkdev(clk, NULL, "spi0");

	clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
				BIT(9), 0);
	clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");

	clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
				BIT(10), 0);
	clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");

	clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
				BIT(11), 0);
	clk_register_clkdev(clk, NULL, "gpio.6");
	clk_register_clkdev(clk, NULL, "gpio.7");
	clk_register_clkdev(clk, NULL, "gpioblock1");

	clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
				BIT(12), 0);
	clk_register_clkdev(clk, "msp4-pclk", "ab85xx-codec.0");

	/* Peripheral 3 : PRCC P-clocks */
	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
				BIT(0), 0);
	clk_register_clkdev(clk, NULL, "fsmc");

	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
				BIT(1), 0);
	clk_register_clkdev(clk, "apb_pclk", "ssp0");

	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
				BIT(2), 0);
	clk_register_clkdev(clk, "apb_pclk", "ssp1");

	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
				BIT(3), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");

	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
				BIT(4), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi2");

	clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
				BIT(5), 0);
	clk_register_clkdev(clk, "apb_pclk", "ske");
	clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");

	clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
				BIT(6), 0);
	clk_register_clkdev(clk, "apb_pclk", "uart2");

	clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
				BIT(7), 0);
	clk_register_clkdev(clk, "apb_pclk", "sdi5");

	clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
				BIT(8), 0);
	clk_register_clkdev(clk, NULL, "gpio.2");
	clk_register_clkdev(clk, NULL, "gpio.3");
	clk_register_clkdev(clk, NULL, "gpio.4");
	clk_register_clkdev(clk, NULL, "gpio.5");
	clk_register_clkdev(clk, NULL, "gpioblock2");

	clk = clk_reg_prcc_pclk("p3_pclk9", "per3clk", bases[CLKRST3_INDEX],
				BIT(9), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.5");

	clk = clk_reg_prcc_pclk("p3_pclk10", "per3clk", bases[CLKRST3_INDEX],
				BIT(10), 0);
	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.6");

	clk = clk_reg_prcc_pclk("p3_pclk11", "per3clk", bases[CLKRST3_INDEX],
				BIT(11), 0);
	clk_register_clkdev(clk, "apb_pclk", "uart3");

	clk = clk_reg_prcc_pclk("p3_pclk12", "per3clk", bases[CLKRST3_INDEX],
				BIT(12), 0);
	clk_register_clkdev(clk, "apb_pclk", "uart4");

	/* Peripheral 5 : PRCC P-clocks */
	clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
				BIT(0), 0);
	clk_register_clkdev(clk, "usb", "musb-ux500.0");
	clk_register_clkdev(clk, "usbclk", "ab-iddet.0");

	clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
				BIT(1), 0);
	clk_register_clkdev(clk, NULL, "gpio.8");
	clk_register_clkdev(clk, NULL, "gpioblock3");

	/* Peripheral 6 : PRCC P-clocks */
	clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
				BIT(0), 0);
	clk_register_clkdev(clk, "apb_pclk", "rng");

	clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
				BIT(1), 0);
	clk_register_clkdev(clk, NULL, "cryp0");
	clk_register_clkdev(clk, NULL, "cryp1");

	clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
				BIT(2), 0);
	clk_register_clkdev(clk, NULL, "hash0");

	clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
				BIT(3), 0);
	clk_register_clkdev(clk, NULL, "pka");

	clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
				BIT(4), 0);
	clk_register_clkdev(clk, NULL, "db8540-hash1");

	clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
				BIT(5), 0);
	clk_register_clkdev(clk, NULL, "cfgreg");

	clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
				BIT(6), 0);
	clk_register_clkdev(clk, "apb_pclk", "mtu0");

	clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
				BIT(7), 0);
	clk_register_clkdev(clk, "apb_pclk", "mtu1");

	/*
	 * PRCC K-clocks  ==> see table PRCC_PCKEN/PRCC_KCKEN
	 * This differs from the internal implementation:
	 * We don't use the PERPIH[n| clock as parent, since those _should_
	 * only be used as parents for the P-clocks.
	 * TODO: "parentjoin" with corresponding P-clocks for all K-clocks.
	 */

	/* Peripheral 1 : PRCC K-clocks */
	clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
			bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "uart0");

	clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
			bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "uart1");

	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
			bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.1");

	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
			bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "msp0");
	clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.0");

	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
			bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "msp1");
	clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.1");

	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmchclk",
			bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi0");

	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
			bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.2");

	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
			bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "slimbus0");

	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
			bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.4");

	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
			bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "msp3");
	clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.3");

	/* Peripheral 2 : PRCC K-clocks */
	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
			bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.3");

	clk = clk_reg_prcc_kclk("p2_pwl_kclk", "rtc32k",
			bases[CLKRST2_INDEX], BIT(1), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "pwl");

	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmchclk",
			bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi4");

	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
			bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "msp2");
	clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.2");

	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmchclk",
			bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi1");

	clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
			bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi3");

	clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
			bases[CLKRST2_INDEX], BIT(6),
			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
	clk_register_clkdev(clk, "hsir_hsirxclk", "ste_hsi.0");

	clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
			bases[CLKRST2_INDEX], BIT(7),
			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
	clk_register_clkdev(clk, "hsit_hsitxclk", "ste_hsi.0");

	/* Should only be 9540, but might be added for 85xx as well */
	clk = clk_reg_prcc_kclk("p2_msp4_kclk", "msp02clk",
			bases[CLKRST2_INDEX], BIT(9), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "msp4");
	clk_register_clkdev(clk, "msp4", "ab85xx-codec.0");

	/* Peripheral 3 : PRCC K-clocks */
	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
			bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "ssp0");

	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
			bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "ssp1");

	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
			bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.0");

	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmchclk",
			bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi2");

	clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
			bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "ske");
	clk_register_clkdev(clk, NULL, "nmk-ske-keypad");

	clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
			bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "uart2");

	clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
			bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "sdi5");

	clk = clk_reg_prcc_kclk("p3_i2c5_kclk", "i2cclk",
			bases[CLKRST3_INDEX], BIT(8), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.5");

	clk = clk_reg_prcc_kclk("p3_i2c6_kclk", "i2cclk",
			bases[CLKRST3_INDEX], BIT(9), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "nmk-i2c.6");

	clk = clk_reg_prcc_kclk("p3_uart3_kclk", "uartclk",
			bases[CLKRST3_INDEX], BIT(10), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "uart3");

	clk = clk_reg_prcc_kclk("p3_uart4_kclk", "uartclk",
			bases[CLKRST3_INDEX], BIT(11), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "uart4");

	/* Peripheral 6 : PRCC K-clocks */
	clk = clk_reg_prcc_kclk("p6_rng_kclk", "rngclk",
			bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
	clk_register_clkdev(clk, NULL, "rng");
}