void __init vexpress_clk_init(void __iomem *sp810_base) { struct clk *clk; int i; clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL, CLK_IS_ROOT, 0); WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL)); clk = clk_register_fixed_rate(NULL, "v2m:clk_24mhz", NULL, CLK_IS_ROOT, 24000000); for (i = 0; i < ARRAY_SIZE(vexpress_clk_24mhz_periphs); i++) WARN_ON(clk_register_clkdev(clk, NULL, vexpress_clk_24mhz_periphs[i])); clk = clk_register_fixed_rate(NULL, "v2m:refclk32khz", NULL, CLK_IS_ROOT, 32768); WARN_ON(clk_register_clkdev(clk, NULL, "v2m:wdt")); clk = clk_register_fixed_rate(NULL, "v2m:refclk1mhz", NULL, CLK_IS_ROOT, 1000000); vexpress_sp810_init(sp810_base); for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++) WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i], clk)); WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0], "v2m-timer0", "sp804")); WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[1], "v2m-timer1", "sp804")); }
static void __init atlas6_clk_init(struct device_node *np) { struct device_node *rscnp; int i; rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc"); sirfsoc_rsc_vbase = of_iomap(rscnp, 0); if (!sirfsoc_rsc_vbase) panic("unable to map rsc registers\n"); of_node_put(rscnp); sirfsoc_clk_vbase = of_iomap(np, 0); if (!sirfsoc_clk_vbase) panic("unable to map clkc registers\n"); /* These are always available (RTC and 26MHz OSC)*/ atlas6_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, CLK_IS_ROOT, 32768); atlas6_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, CLK_IS_ROOT, 26000000); for (i = pll1; i < maxclk; i++) { atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]); BUG_ON(!atlas6_clks[i]); } clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu"); clk_register_clkdev(atlas6_clks[io], NULL, "io"); clk_register_clkdev(atlas6_clks[mem], NULL, "mem"); clk_register_clkdev(atlas6_clks[mem], NULL, "osc"); clk_data.clks = atlas6_clks; clk_data.clk_num = maxclk; of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); }
static void __init v2m_clk_init(void) { struct clk *clk; int i; clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL, CLK_IS_ROOT, 0); WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL)); clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL, CLK_IS_ROOT, 32768); for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++) WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i])); clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL, CLK_IS_ROOT, 1000000); WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804")); WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804")); clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1); for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++) WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i])); clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL, CLK_IS_ROOT, 24000000); for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++) WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i])); }
/* * These are fixed clocks. They're probably not all root clocks and it may * be possible to turn them on and off but until this is mapped out better * it's the only way they can be used. */ void __init bcm2835_init_clocks(void) { struct clk *clk; int ret; clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 126000000); if (IS_ERR(clk)) pr_err("apb_pclk not registered\n"); clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT, 3000000); if (IS_ERR(clk)) pr_err("uart0_pclk not registered\n"); ret = clk_register_clkdev(clk, NULL, "20201000.uart"); if (ret) pr_err("uart0_pclk alias not registered\n"); clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, CLK_IS_ROOT, 125000000); if (IS_ERR(clk)) pr_err("uart1_pclk not registered\n"); ret = clk_register_clkdev(clk, NULL, "20215000.uart"); if (ret) pr_err("uart1_pclk alias not registered\n"); }
void __init mvebu_coreclk_setup(struct device_node *np, const struct coreclk_soc_desc *desc) { const char *tclk_name = "tclk"; const char *cpuclk_name = "cpuclk"; void __iomem *base; unsigned long rate; int n; base = of_iomap(np, 0); if (WARN_ON(!base)) return; /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ clk_data.clk_num = 2 + desc->num_ratios; clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), GFP_KERNEL); if (WARN_ON(!clk_data.clks)) { iounmap(base); return; } /* Register TCLK */ of_property_read_string_index(np, "clock-output-names", 0, &tclk_name); rate = desc->get_tclk_freq(base); clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, CLK_IS_ROOT, rate); WARN_ON(IS_ERR(clk_data.clks[0])); /* Register CPU clock */ of_property_read_string_index(np, "clock-output-names", 1, &cpuclk_name); rate = desc->get_cpu_freq(base); clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, CLK_IS_ROOT, rate); WARN_ON(IS_ERR(clk_data.clks[1])); /* Register fixed-factor clocks derived from CPU clock */ for (n = 0; n < desc->num_ratios; n++) { const char *rclk_name = desc->ratios[n].name; int mult, div; of_property_read_string_index(np, "clock-output-names", 2+n, &rclk_name); desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div); clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name, cpuclk_name, 0, mult, div); WARN_ON(IS_ERR(clk_data.clks[2+n])); }; /* SAR register isn't needed anymore */ iounmap(base); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); }
/* * realview_clk_init() - set up the RealView clock tree */ void __init realview_clk_init(void *sysbase, bool is_pb1176) { struct clk *clk; /* APB clock dummy */ clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); clk_register_clkdev(clk, "apb_pclk", NULL); /* 24 MHz clock */ clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT, 24000000); clk_register_clkdev(clk, NULL, "dev:uart0"); clk_register_clkdev(clk, NULL, "dev:uart1"); clk_register_clkdev(clk, NULL, "dev:uart2"); clk_register_clkdev(clk, NULL, "fpga:kmi0"); clk_register_clkdev(clk, NULL, "fpga:kmi1"); clk_register_clkdev(clk, NULL, "fpga:mmc0"); clk_register_clkdev(clk, NULL, "dev:ssp0"); if (is_pb1176) { /* * UART3 is on the dev chip in PB1176 * UART4 only exists in PB1176 */ clk_register_clkdev(clk, NULL, "dev:uart3"); clk_register_clkdev(clk, NULL, "dev:uart4"); } else clk_register_clkdev(clk, NULL, "fpga:uart3"); /* FIXME: Dummy clocks to force match with device tree node names */ clk_register_clkdev(clk, NULL, "kmi0"); clk_register_clkdev(clk, NULL, "kmi1"); /* 1 MHz clock */ clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT, 1000000); clk_register_clkdev(clk, NULL, "sp804"); /* ICST VCO clock */ if (is_pb1176) clk = icst_clk_register(NULL, &realview_osc0_desc, sysbase); else clk = icst_clk_register(NULL, &realview_osc4_desc, sysbase); clk_register_clkdev(clk, NULL, "dev:clcd"); clk_register_clkdev(clk, NULL, "issp:clcd"); /* FIXME: Dummy clocks to force match with device tree node names */ clk_register_clkdev(clk, NULL, "clcd"); }
int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, int nums, struct hisi_clock_data *data) { struct clk *clk; int i; for (i = 0; i < nums; i++) { clk = clk_register_fixed_rate(NULL, clks[i].name, clks[i].parent_name, clks[i].flags, clks[i].fixed_rate); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); goto err; } data->clk_data.clks[clks[i].id] = clk; } return 0; err: while (i--) clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]); return PTR_ERR(clk); }
/** * of_fixed_clk_setup() - Setup function for simple fixed rate clock */ void of_fixed_clk_setup(struct device_node *node) { struct clk *clk; const char *clk_name = node->name; u32 rate = 0; if (of_property_read_u32(node, "clock-frequency", &rate)) { pr_err("%s Fixed rate clock <%s> must have a clock rate property\n", __func__, node->name); return; } if (of_property_read_string(node, "clock-output-names", &clk_name)) { pr_err("%s Fixed rate clock <%s> must have a clock name property\n", __func__, node->name); return; } clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate); if (!IS_ERR(clk)) of_clk_add_provider(node, of_clk_src_simple_get, clk); #ifdef CONFIG_HI3630_CLK clk_register_clkdev(clk, clk_name, NULL); #endif }
/* * ccu_osc_clk_init * ccu is in same PCI device with PMU. CCU address is at offset 0x800. * ccu's inialization is called from PMU init. */ int ccu_osc_clk_init(void __iomem *ccubase) { struct clk *clk; int i, ret; char name[12]; pr_debug("%s entry\n", __func__); clk = clk_register_fixed_rate(NULL, "clk-osc", NULL, CLK_IS_ROOT, OSC_CLOCK_RATE); if (IS_ERR(clk)) { pr_err("%s:clk register fail.\n", __func__); return -1; } clk_register_clkdev(clk, "clk-osc", NULL); for (i = 0; i < OSC_CLOCK_COUNT; i++) { memset(name, 0, sizeof(name)); sprintf(name, "osc.%d", i); clk = ccu_osc_clk_register(name, "clk-osc", ccubase + CCU_OSC_CTL_OFF + i * 4, i); if (!IS_ERR(clk)) ret = clk_register_clkdev(clk, name, NULL); } return 0; }
void __init clk_init(void) { tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, orion5x_tclk); orion_clkdev_init(tclk); }
static struct clk * __init meson_clk_register_fixed_rate(const struct clk_conf *clk_conf, void __iomem *clk_base) { struct clk *clk; const struct fixed_rate_conf *fixed_rate_conf; const struct parm *r; unsigned long rate; u32 reg; fixed_rate_conf = &clk_conf->conf.fixed_rate; rate = fixed_rate_conf->rate; if (!rate) { r = &fixed_rate_conf->rate_parm; reg = readl(clk_base + clk_conf->reg_off + r->reg_off); rate = PARM_GET(r->width, r->shift, reg); } rate *= 1000000; clk = clk_register_fixed_rate(NULL, clk_conf->clk_name, clk_conf->num_parents ? clk_conf->clks_parent[0] : NULL, clk_conf->flags, rate); return clk; }
/* register a list of fixed clocks */ void __init amlogic_clk_register_fixed_rate( struct amlogic_fixed_rate_clock *list, unsigned int nr_clk) { struct clk *clk; unsigned int idx, ret; for (idx = 0; idx < nr_clk; idx++, list++) { clk = clk_register_fixed_rate(NULL, list->name, list->parent_name, list->flags, list->fixed_rate); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, list->name); continue; } amlogic_clk_add_lookup(clk, list->id); /* * Unconditionally add a clock lookup for the fixed rate clocks. * There are not many of these on any of Amlogic platforms. */ ret = clk_register_clkdev(clk, list->name, NULL); if (ret) pr_err("%s: failed to register clock lookup for %s", __func__, list->name); } }
static void __init spear320_clk_init(void __iomem *soc_config_base) { struct clk *clk; clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, CLK_IS_ROOT, 125000000); clk_register_clkdev(cl
static int dw_i2c_acpi_configure(struct platform_device *pdev) { struct dw_i2c_dev *dev = platform_get_drvdata(pdev); const struct acpi_device_id *id; dev->adapter.nr = -1; dev->tx_fifo_depth = 32; dev->rx_fifo_depth = 32; /* * Try to get SDA hold time and *CNT values from an ACPI method if * it exists for both supported speed modes. */ dw_i2c_acpi_params(pdev, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, NULL); dw_i2c_acpi_params(pdev, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &dev->sda_hold_time); /* * Provide a way for Designware I2C host controllers that are not * based on Intel LPSS to specify their input clock frequency via * id->driver_data. */ id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev); if (id && id->driver_data) clk_register_fixed_rate(&pdev->dev, dev_name(&pdev->dev), NULL, CLK_IS_ROOT, id->driver_data); return 0; }
void __init socfpga_init_clocks(void) { struct clk *clk; clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK); clk_register_clkdev(clk, "osc1_clk", NULL); clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK); clk_register_clkdev(clk, "mpu_clk", NULL); clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2); clk_register_clkdev(clk, "main_clk", NULL); clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2); clk_register_clkdev(clk, "dbg_base_clk", NULL); clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK); clk_register_clkdev(clk, "main_qspi_clk", NULL); clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK); clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL); clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK); clk_register_clkdev(clk, "s2f_usr_clk", NULL); }
static struct clk *sysclk_from_fixed(struct device_node *node, const char *name) { u32 rate; if (of_property_read_u32(node, "clock-frequency", &rate)) return ERR_PTR(-ENODEV); return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); }
int __init da850_register_sata_refclk(int rate) { struct clk *clk; clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate); if (IS_ERR(clk)) return PTR_ERR(clk); return clk_register_clkdev(clk, "refclk", "ahci_da850"); }
struct clk __init *bcm2708_clk_register(const char *name, unsigned long fixed_rate) { struct clk *clk; clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, fixed_rate); if (IS_ERR(clk)) pr_err("%s not registered\n", name); return clk; }
static void __init dove_clk_init(void) { struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; struct clk *xor0, *xor1, *ge, *gephy; tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, dove_tclk); usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA); i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0); i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1); crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO); ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97); pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA); xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0); xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1); gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY); ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE); orion_clkdev_add(NULL, "orion_spi.0", tclk); orion_clkdev_add(NULL, "orion_spi.1", tclk); orion_clkdev_add(NULL, "orion_wdt", tclk); orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); orion_clkdev_add(NULL, "orion-ehci.0", usb0); orion_clkdev_add(NULL, "orion-ehci.1", usb1); orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge); orion_clkdev_add(NULL, "sata_mv.0", sata); orion_clkdev_add("0", "pcie", pex0); orion_clkdev_add("1", "pcie", pex1); orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); orion_clkdev_add(NULL, "orion_nand", nand); orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); orion_clkdev_add(NULL, "mvebu-audio.0", i2s0); orion_clkdev_add(NULL, "mvebu-audio.1", i2s1); orion_clkdev_add(NULL, "mv_crypto", crypto); orion_clkdev_add(NULL, "dove-ac97", ac97); orion_clkdev_add(NULL, "dove-pdma", pdma); orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0); orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1); }
/* * integrator_clk_init() - set up the integrator clock tree * @is_cp: pass true if it's the Integrator/CP else AP is assumed */ void __init integrator_clk_init(bool is_cp) { struct clk *clk; /* APB clock dummy */ clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); clk_register_clkdev(clk, "apb_pclk", NULL); /* UART reference clock */ clk = clk_register_fixed_rate(NULL, "uartclk", NULL, CLK_IS_ROOT, 14745600); clk_register_clkdev(clk, NULL, "uart0"); clk_register_clkdev(clk, NULL, "uart1"); if (is_cp) clk_register_clkdev(clk, NULL, "mmci"); /* 24 MHz clock */ clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT, 24000000); clk_register_clkdev(clk, NULL, "kmi0"); clk_register_clkdev(clk, NULL, "kmi1"); if (!is_cp) clk_register_clkdev(clk, NULL, "ap_timer"); if (!is_cp) return; /* 1 MHz clock */ clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT, 1000000); clk_register_clkdev(clk, NULL, "sp804"); /* ICST VCO clock used on the Integrator/CP CLCD */ clk = icst_clk_register(NULL, &cp_icst_desc, "icst", __io_address(INTEGRATOR_HDR_BASE)); clk_register_clkdev(clk, NULL, "clcd"); }
/** * of_fixed_clk_setup() - Setup function for simple fixed rate clock */ void of_fixed_clk_setup(struct device_node *node) { struct clk *clk; const char *clk_name = node->name; u32 rate; if (of_property_read_u32(node, "clock-frequency", &rate)) return; of_property_read_string(node, "clock-output-names", &clk_name); clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate); if (!IS_ERR(clk)) of_clk_add_provider(node, of_clk_src_simple_get, clk); }
static int acpi_apd_setup(struct apd_private_data *pdata) { const struct apd_device_desc *dev_desc = pdata->dev_desc; struct clk *clk = ERR_PTR(-ENODEV); if (dev_desc->fixed_clk_rate) { clk = clk_register_fixed_rate(&pdata->adev->dev, dev_name(&pdata->adev->dev), NULL, 0, dev_desc->fixed_clk_rate); clk_register_clkdev(clk, NULL, dev_name(&pdata->adev->dev)); pdata->clk = clk; } return 0; }
void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, int nums, struct hisi_clock_data *data) { struct clk *clk; int i; for (i = 0; i < nums; i++) { clk = clk_register_fixed_rate(NULL, clks[i].name, clks[i].parent_name, clks[i].flags, clks[i].fixed_rate); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); continue; } data->clk_data.clks[clks[i].id] = clk; } }
static int lpt_clk_probe(struct platform_device *pdev) { struct lpss_clk_data *drvdata; struct clk *clk; drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; /* LPSS free running clock */ drvdata->name = "lpss_clk"; clk = clk_register_fixed_rate(&pdev->dev, drvdata->name, NULL, 0, 100000000); if (IS_ERR(clk)) return PTR_ERR(clk); drvdata->clk = clk; platform_set_drvdata(pdev, drvdata); return 0; }
void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit, struct mmp_param_fixed_rate_clk *clks, int size) { int i; struct clk *clk; for (i = 0; i < size; i++) { clk = clk_register_fixed_rate(NULL, clks[i].name, clks[i].parent_name, clks[i].flags, clks[i].fixed_rate); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); continue; } if (clks[i].id) unit->clk_table[clks[i].id] = clk; } }
static struct clk *ak4642_of_parse_mcko(struct device *dev) { struct device_node *np = dev->of_node; struct clk *clk; const char *clk_name = np->name; const char *parent_clk_name = NULL; u32 rate; if (of_property_read_u32(np, "clock-frequency", &rate)) return NULL; if (of_property_read_bool(np, "clocks")) parent_clk_name = of_clk_get_parent_name(np, 0); of_property_read_string(np, "clock-output-names", &clk_name); clk = clk_register_fixed_rate(dev, clk_name, parent_clk_name, 0, rate); if (!IS_ERR(clk)) of_clk_add_provider(np, of_clk_src_simple_get, clk); return clk; }
void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys, phys_addr_t apbc_phys, phys_addr_t apbcp_phys) { struct clk *clk; struct clk *uart_pll; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbcp_base; void __iomem *apbc_base; mpmu_base = ioremap(mpmu_phys, SZ_4K); if (mpmu_base == NULL) { pr_err("error to ioremap MPMU base\n"); return; } apmu_base = ioremap(apmu_phys, SZ_4K); if (apmu_base == NULL) { pr_err("error to ioremap APMU base\n"); return; } apbcp_base = ioremap(apbcp_phys, SZ_4K); if (apbcp_base == NULL) { pr_err("error to ioremap APBC extension base\n"); return; } apbc_base = ioremap(apbc_phys, SZ_4K); if (apbc_base == NULL) { pr_err("error to ioremap APBC base\n"); return; } clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); clk_register_clkdev(clk, "clk32", NULL); clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); clk_register_clkdev(clk, "vctcxo", NULL); clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); clk_register_clkdev(clk, "pll1", NULL); clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_2", NULL); clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_4", NULL); clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_8", NULL); clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_16", NULL); clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", CLK_SET_RATE_PARENT, 1, 3); clk_register_clkdev(clk, "pll1_6", NULL); clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_12", NULL); clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_24", NULL); clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_48", NULL); clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_96", NULL); clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", CLK_SET_RATE_PARENT, 1, 13); clk_register_clkdev(clk, "pll1_13", NULL); clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", CLK_SET_RATE_PARENT, 2, 3); clk_register_clkdev(clk, "pll1_13_1_5", NULL); clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", CLK_SET_RATE_PARENT, 2, 3); clk_register_clkdev(clk, "pll1_2_1_5", NULL); clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", CLK_SET_RATE_PARENT, 3, 16); clk_register_clkdev(clk, "pll1_3_16", NULL); uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0, mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl), &clk_lock); clk_set_rate(uart_pll, 14745600); clk_register_clkdev(uart_pll, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", apbc_base + APBC_TWSI0, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); clk = mmp_clk_register_apbc("gpio", "vctcxo", apbc_base + APBC_GPIO, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp-gpio"); clk = mmp_clk_register_apbc("kpc", "clk32", apbc_base + APBC_KPC, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa27x-keypad"); clk = mmp_clk_register_apbc("rtc", "clk32", apbc_base + APBC_RTC, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "sa1100-rtc"); clk = mmp_clk_register_apbc("pwm0", "pll1_48", apbc_base + APBC_PWM0, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa910-pwm.0"); clk = mmp_clk_register_apbc("pwm1", "pll1_48", apbc_base + APBC_PWM1, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa910-pwm.1"); clk = mmp_clk_register_apbc("pwm2", "pll1_48", apbc_base + APBC_PWM2, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa910-pwm.2"); clk = mmp_clk_register_apbc("pwm3", "pll1_48", apbc_base + APBC_PWM3, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa910-pwm.3"); clk = clk_register_mux(NULL, "uart0_mux", uart_parent, ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); clk_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", apbc_base + APBC_UART0, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); clk = clk_register_mux(NULL, "uart1_mux", uart_parent, ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); clk_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", apbc_base + APBC_UART1, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); clk = clk_register_mux(NULL, "uart2_mux", uart_parent, ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); clk_set_parent(clk, uart_pll); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", apbcp_base + APBCP_UART2, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp-ssp.0"); clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); clk_register_clkdev(clk, "ssp_mux.1", NULL); clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp-ssp.1"); clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, 0x19b, &clk_lock); clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); clk_register_clkdev(clk, "sdh0_mux", NULL); clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0, 0x1b, &clk_lock); clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); clk_register_clkdev(clk, "sdh1_mux", NULL); clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1, 0x1b, &clk_lock); clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, 0x9, &clk_lock); clk_register_clkdev(clk, "usb_clk", NULL); clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, 0x12, &clk_lock); clk_register_clkdev(clk, "sph_clk", NULL); clk = clk_register_mux(NULL, "disp0_mux", disp_parent, ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); clk_register_clkdev(clk, "disp_mux.0", NULL); clk = mmp_clk_register_apmu("disp0", "disp0_mux", apmu_base + APMU_DISP0, 0x1b, &clk_lock); clk_register_clkdev(clk, NULL, "mmp-disp.0"); clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); clk_register_clkdev(clk, "ccic_mux.0", NULL); clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", apmu_base + APMU_CCIC0, 0x1b, &clk_lock); clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, ARRAY_SIZE(ccic_phy_parent), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", apmu_base + APMU_CCIC0, 0x24, &clk_lock); clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 10, 5, 0, &clk_lock); clk_register_clkdev(clk, "sphyclk_div", NULL); clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", apmu_base + APMU_CCIC0, 0x300, &clk_lock); clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); }
void __init mmp2_clk_init(void) { struct clk *clk; struct clk *vctcxo; void __iomem *mpmu_base; void __iomem *apmu_base; void __iomem *apbc_base; mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K); if (mpmu_base == NULL) { pr_err("error to ioremap MPMU base\n"); return; } apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K); if (apmu_base == NULL) { pr_err("error to ioremap APMU base\n"); return; } apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K); if (apbc_base == NULL) { pr_err("error to ioremap APBC base\n"); return; } clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); clk_register_clkdev(clk, "clk32", NULL); vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, 26000000); clk_register_clkdev(vctcxo, "vctcxo", NULL); clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, 800000000); clk_register_clkdev(clk, "pll1", NULL); clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT, 480000000); clk_register_clkdev(clk, "usb_pll", NULL); clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT, 960000000); clk_register_clkdev(clk, "pll2", NULL); clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_2", NULL); clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_4", NULL); clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_8", NULL); clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_16", NULL); clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4", CLK_SET_RATE_PARENT, 1, 5); clk_register_clkdev(clk, "pll1_20", NULL); clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1", CLK_SET_RATE_PARENT, 1, 3); clk_register_clkdev(clk, "pll1_3", NULL); clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_6", NULL); clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll1_12", NULL); clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll2_2", NULL); clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll2_4", NULL); clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll2_8", NULL); clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll2_16", NULL); clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2", CLK_SET_RATE_PARENT, 1, 3); clk_register_clkdev(clk, "pll2_3", NULL); clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll2_6", NULL); clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "pll2_12", NULL); clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "vctcxo_2", NULL); clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "vctcxo_4", NULL); clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0, mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl, ARRAY_SIZE(uart_factor_tbl)); clk_set_rate(clk, 14745600); clk_register_clkdev(clk, "uart_pll", NULL); clk = mmp_clk_register_apbc("twsi0", "vctcxo", apbc_base + APBC_TWSI0, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); clk = mmp_clk_register_apbc("twsi1", "vctcxo", apbc_base + APBC_TWSI1, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); clk = mmp_clk_register_apbc("twsi2", "vctcxo", apbc_base + APBC_TWSI2, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2"); clk = mmp_clk_register_apbc("twsi3", "vctcxo", apbc_base + APBC_TWSI3, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3"); clk = mmp_clk_register_apbc("twsi4", "vctcxo", apbc_base + APBC_TWSI4, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4"); clk = mmp_clk_register_apbc("twsi5", "vctcxo", apbc_base + APBC_TWSI5, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5"); clk = mmp_clk_register_apbc("gpio", "vctcxo", apbc_base + APBC_GPIO, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp2-gpio"); clk = mmp_clk_register_apbc("kpc", "clk32", apbc_base + APBC_KPC, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa27x-keypad"); clk = mmp_clk_register_apbc("rtc", "clk32", apbc_base + APBC_RTC, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp-rtc"); clk = mmp_clk_register_apbc("pwm0", "vctcxo", apbc_base + APBC_PWM0, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp2-pwm.0"); clk = mmp_clk_register_apbc("pwm1", "vctcxo", apbc_base + APBC_PWM1, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp2-pwm.1"); clk = mmp_clk_register_apbc("pwm2", "vctcxo", apbc_base + APBC_PWM2, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp2-pwm.2"); clk = mmp_clk_register_apbc("pwm3", "vctcxo", apbc_base + APBC_PWM3, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp2-pwm.3"); clk = clk_register_mux(NULL, "uart0_mux", uart_parent, ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); clk_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("uart0", "uart0_mux", apbc_base + APBC_UART0, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); clk = clk_register_mux(NULL, "uart1_mux", uart_parent, ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); clk_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.1", NULL); clk = mmp_clk_register_apbc("uart1", "uart1_mux", apbc_base + APBC_UART1, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); clk = clk_register_mux(NULL, "uart2_mux", uart_parent, ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); clk_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.2", NULL); clk = mmp_clk_register_apbc("uart2", "uart2_mux", apbc_base + APBC_UART2, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); clk = clk_register_mux(NULL, "uart3_mux", uart_parent, ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); clk_set_parent(clk, vctcxo); clk_register_clkdev(clk, "uart_mux.3", NULL); clk = mmp_clk_register_apbc("uart3", "uart3_mux", apbc_base + APBC_UART3, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "pxa2xx-uart.3"); clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); clk_register_clkdev(clk, "uart_mux.0", NULL); clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp-ssp.0"); clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); clk_register_clkdev(clk, "ssp_mux.1", NULL); clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp-ssp.1"); clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); clk_register_clkdev(clk, "ssp_mux.2", NULL); clk = mmp_clk_register_apbc("ssp2", "ssp2_mux", apbc_base + APBC_SSP2, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp-ssp.2"); clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); clk_register_clkdev(clk, "ssp_mux.3", NULL); clk = mmp_clk_register_apbc("ssp3", "ssp3_mux", apbc_base + APBC_SSP3, 10, 0, &clk_lock); clk_register_clkdev(clk, NULL, "mmp-ssp.3"); clk = clk_register_mux(NULL, "sdh_mux", sdh_parent, ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock); clk_register_clkdev(clk, "sdh_mux", NULL); clk = clk_register_divider(NULL, "sdh_div", "sdh_mux", CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); clk_register_clkdev(clk, "sdh_div", NULL); clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0, 0x1b, &clk_lock); clk_register_clkdev(clk, NULL, "sdhci-pxav3.0"); clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1, 0x1b, &clk_lock); clk_register_clkdev(clk, NULL, "sdhci-pxav3.1"); clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2, 0x1b, &clk_lock); clk_register_clkdev(clk, NULL, "sdhci-pxav3.2"); clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3, 0x1b, &clk_lock); clk_register_clkdev(clk, NULL, "sdhci-pxav3.3"); clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, 0x9, &clk_lock); clk_register_clkdev(clk, "usb_clk", NULL); clk = clk_register_mux(NULL, "disp0_mux", disp_parent, ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock); clk_register_clkdev(clk, "disp_mux.0", NULL); clk = clk_register_divider(NULL, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); clk_register_clkdev(clk, "disp_div.0", NULL); clk = mmp_clk_register_apmu("disp0", "disp0_div", apmu_base + APMU_DISP0, 0x1b, &clk_lock); clk_register_clkdev(clk, NULL, "mmp-disp.0"); clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0, apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock); clk_register_clkdev(clk, "disp_sphy_div.0", NULL); clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div", apmu_base + APMU_DISP0, 0x1024, &clk_lock); clk_register_clkdev(clk, "disp_sphy.0", NULL); clk = clk_register_mux(NULL, "disp1_mux", disp_parent, ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock); clk_register_clkdev(clk, "disp_mux.1", NULL); clk = clk_register_divider(NULL, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); clk_register_clkdev(clk, "disp_div.1", NULL); clk = mmp_clk_register_apmu("disp1", "disp1_div", apmu_base + APMU_DISP1, 0x1b, &clk_lock); clk_register_clkdev(clk, NULL, "mmp-disp.1"); clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo", apmu_base + APMU_CCIC0, 0x1800, &clk_lock); clk_register_clkdev(clk, "ccic_arbiter", NULL); clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); clk_register_clkdev(clk, "ccic_mux.0", NULL); clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux", CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); clk_register_clkdev(clk, "ccic_div.0", NULL); clk = mmp_clk_register_apmu("ccic0", "ccic0_div", apmu_base + APMU_CCIC0, 0x1b, &clk_lock); clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div", apmu_base + APMU_CCIC0, 0x24, &clk_lock); clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div", CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 10, 5, 0, &clk_lock); clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0"); clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", apmu_base + APMU_CCIC0, 0x300, &clk_lock); clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent, ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock); clk_register_clkdev(clk, "ccic_mux.1", NULL); clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux", CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); clk_register_clkdev(clk, "ccic_div.1", NULL); clk = mmp_clk_register_apmu("ccic1", "ccic1_div", apmu_base + APMU_CCIC1, 0x1b, &clk_lock); clk_register_clkdev(clk, "fnclk", "mmp-ccic.1"); clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div", apmu_base + APMU_CCIC1, 0x24, &clk_lock); clk_register_clkdev(clk, "phyclk", "mmp-ccic.1"); clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div", CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, 10, 5, 0, &clk_lock); clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1"); clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div", apmu_base + APMU_CCIC1, 0x300, &clk_lock); clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1"); }
void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, u32 clkrst5_base, u32 clkrst6_base) { struct prcmu_fw_version *fw_version; const char *sgaclk_parent = NULL; struct clk *clk; /* Clock sources */ clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, CLK_IS_ROOT|CLK_IGNORE_UNUSED); clk_register_clkdev(clk, "soc0_pll", NULL); clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, CLK_IS_ROOT|CLK_IGNORE_UNUSED); clk_register_clkdev(clk, "soc1_pll", NULL); clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, CLK_IS_ROOT|CLK_IGNORE_UNUSED); clk_register_clkdev(clk, "ddr_pll", NULL); /* FIXME: Add sys, ulp and int clocks here. */ clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL", CLK_IS_ROOT|CLK_IGNORE_UNUSED, 32768); clk_register_clkdev(clk, "clk32k", NULL); clk_register_clkdev(clk, "apb_pclk", "rtc-pl031"); /* PRCMU clocks */ fw_version = prcmu_get_fw_version(); if (fw_version != NULL) { switch (fw_version->project) { case PRCMU_FW_PROJECT_U8500_C2: case PRCMU_FW_PROJECT_U8520: case PRCMU_FW_PROJECT_U8420: sgaclk_parent = "soc0_pll"; break; default: break; } } if (sgaclk_parent) clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent, PRCMU_SGACLK, 0); else clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "mali"); clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "UART"); clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "MSP02"); clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "MSP1"); clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "I2C"); clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "slim"); clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "PERIPH1"); clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "PERIPH2"); clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "PERIPH3"); clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "PERIPH5"); clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "PERIPH6"); clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "PERIPH7"); clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, CLK_IS_ROOT|CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "lcd"); clk_register_clkdev(clk, "lcd", "mcde"); clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "bml"); clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, CLK_IS_ROOT|CLK_SET_RATE_GATE); clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, CLK_IS_ROOT|CLK_SET_RATE_GATE); clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, CLK_IS_ROOT|CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "hdmi"); clk_register_clkdev(clk, "hdmi", "mcde"); clk = clk_reg_prcmu_scalable("apeatclk", NULL, PRCMU_APEATCLK, 0, CLK_IS_ROOT|CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "apeat"); clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0, CLK_IS_ROOT|CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "apetrace"); clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "mcde"); clk_register_clkdev(clk, "mcde", "mcde"); clk_register_clkdev(clk, "dsisys", "dsilink.0"); clk_register_clkdev(clk, "dsisys", "dsilink.1"); clk_register_clkdev(clk, "dsisys", "dsilink.2"); clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "ipi2"); clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "dsialt"); clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "dma40.0"); clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "b2r2"); clk_register_clkdev(clk, NULL, "b2r2_core"); clk_register_clkdev(clk, NULL, "U8500-B2R2.0"); clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, CLK_IS_ROOT|CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "tv"); clk_register_clkdev(clk, "tv", "mcde"); clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "SSP"); clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "rngclk"); clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "uicc"); clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); clk_register_clkdev(clk, NULL, "mtu0"); clk_register_clkdev(clk, NULL, "mtu1"); clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, 100000000, CLK_IS_ROOT|CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdmmc"); clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); clk_register_clkdev(clk, "dsihs2", "mcde"); clk_register_clkdev(clk, "dsihs2", "dsilink.2"); clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); clk_register_clkdev(clk, "dsihs0", "mcde"); clk_register_clkdev(clk, "dsihs0", "dsilink.0"); clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); clk_register_clkdev(clk, "dsihs1", "mcde"); clk_register_clkdev(clk, "dsihs1", "dsilink.1"); clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); clk_register_clkdev(clk, "dsilp0", "dsilink.0"); clk_register_clkdev(clk, "dsilp0", "mcde"); clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE); clk_register_clkdev(clk, "dsilp1", "dsilink.1"); clk_register_clkdev(clk, "dsilp1", "mcde"); clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE); clk_register_clkdev(clk, "dsilp2", "dsilink.2"); clk_register_clkdev(clk, "dsilp2", "mcde"); clk = clk_reg_prcmu_scalable_rate("armss", NULL, PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED); clk_register_clkdev(clk, "armss", NULL); clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", CLK_IGNORE_UNUSED, 1, 2); clk_register_clkdev(clk, NULL, "smp_twd"); /* * FIXME: Add special handled PRCMU clocks here: * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. * 2. ab9540_clkout1yuv, see clkout0yuv */ /* PRCC P-clocks */ clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base, BIT(0), 0); clk_register_clkdev(clk, "apb_pclk", "uart0"); clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base, BIT(1), 0); clk_register_clkdev(clk, "apb_pclk", "uart1"); clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base, BIT(2), 0); clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1"); clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base, BIT(3), 0); clk_register_clkdev(clk, "apb_pclk", "msp0"); clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0"); clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base, BIT(4), 0); clk_register_clkdev(clk, "apb_pclk", "msp1"); clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1"); clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base, BIT(5), 0); clk_register_clkdev(clk, "apb_pclk", "sdi0"); clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base, BIT(6), 0); clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2"); clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base, BIT(7), 0); clk_register_clkdev(clk, NULL, "spi3"); clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base, BIT(8), 0); clk_register_clkdev(clk, "apb_pclk", "slimbus0"); clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base, BIT(9), 0); clk_register_clkdev(clk, NULL, "gpio.0"); clk_register_clkdev(clk, NULL, "gpio.1"); clk_register_clkdev(clk, NULL, "gpioblock0"); clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base, BIT(10), 0); clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4"); clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base, BIT(11), 0); clk_register_clkdev(clk, "apb_pclk", "msp3"); clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3"); clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base, BIT(0), 0); clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3"); clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base, BIT(1), 0); clk_register_clkdev(clk, NULL, "spi2"); clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base, BIT(2), 0); clk_register_clkdev(clk, NULL, "spi1"); clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base, BIT(3), 0); clk_register_clkdev(clk, NULL, "pwl"); clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base, BIT(4), 0); clk_register_clkdev(clk, "apb_pclk", "sdi4"); clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base, BIT(5), 0); clk_register_clkdev(clk, "apb_pclk", "msp2"); clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2"); clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base, BIT(6), 0); clk_register_clkdev(clk, "apb_pclk", "sdi1"); clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base, BIT(7), 0); clk_register_clkdev(clk, "apb_pclk", "sdi3"); clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base, BIT(8), 0); clk_register_clkdev(clk, NULL, "spi0"); clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base, BIT(9), 0); clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0"); clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base, BIT(10), 0); clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0"); clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base, BIT(11), 0); clk_register_clkdev(clk, NULL, "gpio.6"); clk_register_clkdev(clk, NULL, "gpio.7"); clk_register_clkdev(clk, NULL, "gpioblock1"); clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base, BIT(12), 0); clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, BIT(0), 0); clk_register_clkdev(clk, "fsmc", NULL); clk_register_clkdev(clk, NULL, "smsc911x.0"); clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, BIT(1), 0); clk_register_clkdev(clk, "apb_pclk", "ssp0"); clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base, BIT(2), 0); clk_register_clkdev(clk, "apb_pclk", "ssp1"); clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base, BIT(3), 0); clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0"); clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base, BIT(4), 0); clk_register_clkdev(clk, "apb_pclk", "sdi2"); clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base, BIT(5), 0); clk_register_clkdev(clk, "apb_pclk", "ske"); clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad"); clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base, BIT(6), 0); clk_register_clkdev(clk, "apb_pclk", "uart2"); clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base, BIT(7), 0); clk_register_clkdev(clk, "apb_pclk", "sdi5"); clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base, BIT(8), 0); clk_register_clkdev(clk, NULL, "gpio.2"); clk_register_clkdev(clk, NULL, "gpio.3"); clk_register_clkdev(clk, NULL, "gpio.4"); clk_register_clkdev(clk, NULL, "gpio.5"); clk_register_clkdev(clk, NULL, "gpioblock2"); clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base, BIT(0), 0); clk_register_clkdev(clk, "usb", "musb-ux500.0"); clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base, BIT(1), 0); clk_register_clkdev(clk, NULL, "gpio.8"); clk_register_clkdev(clk, NULL, "gpioblock3"); clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base, BIT(0), 0); clk_register_clkdev(clk, "apb_pclk", "rng"); clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base, BIT(1), 0); clk_register_clkdev(clk, NULL, "cryp0"); clk_register_clkdev(clk, NULL, "cryp1"); clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base, BIT(2), 0); clk_register_clkdev(clk, NULL, "hash0"); clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base, BIT(3), 0); clk_register_clkdev(clk, NULL, "pka"); clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base, BIT(4), 0); clk_register_clkdev(clk, NULL, "hash1"); clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base, BIT(5), 0); clk_register_clkdev(clk, NULL, "cfgreg"); clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base, BIT(6), 0); clk_register_clkdev(clk, "apb_pclk", "mtu0"); clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base, BIT(7), 0); clk_register_clkdev(clk, "apb_pclk", "mtu1"); /* PRCC K-clocks * * FIXME: Some drivers requires PERPIH[n| to be automatically enabled * by enabling just the K-clock, even if it is not a valid parent to * the K-clock. Until drivers get fixed we might need some kind of * "parent muxed join". */ /* Periph1 */ clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", clkrst1_base, BIT(0), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "uart0"); clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", clkrst1_base, BIT(1), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "uart1"); clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", clkrst1_base, BIT(2), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "nmk-i2c.1"); clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", clkrst1_base, BIT(3), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "msp0"); clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0"); clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", clkrst1_base, BIT(4), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "msp1"); clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1"); clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", clkrst1_base, BIT(5), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi0"); clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", clkrst1_base, BIT(6), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "nmk-i2c.2"); clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", clkrst1_base, BIT(8), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "slimbus0"); clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", clkrst1_base, BIT(9), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "nmk-i2c.4"); clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", clkrst1_base, BIT(10), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "msp3"); clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3"); /* Periph2 */ clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", clkrst2_base, BIT(0), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "nmk-i2c.3"); clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", clkrst2_base, BIT(2), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi4"); clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", clkrst2_base, BIT(3), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "msp2"); clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2"); clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", clkrst2_base, BIT(4), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi1"); clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", clkrst2_base, BIT(5), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi3"); /* Note that rate is received from parent. */ clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", clkrst2_base, BIT(6), CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", clkrst2_base, BIT(7), CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); /* Periph3 */ clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", clkrst3_base, BIT(1), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "ssp0"); clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", clkrst3_base, BIT(2), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "ssp1"); clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", clkrst3_base, BIT(3), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "nmk-i2c.0"); clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", clkrst3_base, BIT(4), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi2"); clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", clkrst3_base, BIT(5), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "ske"); clk_register_clkdev(clk, NULL, "nmk-ske-keypad"); clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", clkrst3_base, BIT(6), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "uart2"); clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", clkrst3_base, BIT(7), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi5"); /* Periph6 */ clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", clkrst6_base, BIT(0), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "rng"); }
static int __init sunxi_init_ac100_clocks(void) { struct clk *clk; struct clk *parent; int i; struct periph_init_data *periph; if (arisc_rsb_set_rtsaddr(RSB_DEVICE_SADDR7, RSB_RTSADDR_AC100)) { pr_err("%s err: config codec failed\n", __func__); return -1; } //reigster source for AC100 32K clk = clk_register_fixed_rate(NULL, "32k_rtc", NULL, CLK_IS_ROOT, 32768); clk_register_clkdev(clk, "32k_rtc", NULL); clk = clk_register_fixed_rate(NULL, "4m_adda", NULL, CLK_IS_ROOT, 4000000); clk_register_clkdev(clk, "4m_adda", NULL); sunxi_clk_get_periph_ops(&ac100_clkops); ac100_clkops.prepare = ac100_clkops.enable; ac100_clkops.unprepare = ac100_clkops.disable; ac100_clkops.enable = NULL; ac100_clkops.disable = NULL; ac100_clkops.recalc_rate = sunxi_ac100_recalc_rate; ac100_clkops.round_rate = sunxi_ac100_round_rate; ac100_clkops.set_rate = __sunxi_clk_periph_set_rate; ac100_regops.reg_writel = ac100_writel; ac100_regops.reg_readl = ac100_readl; /* register AC100 clock */ for(i=0; i<ARRAY_SIZE(sunxi_ac100_init); i++) { periph = &sunxi_ac100_init[i]; periph->periph->priv_clkops = &ac100_clkops; periph->periph->priv_regops = &ac100_regops; clk = sunxi_clk_register_periph(periph->name, periph->parent_names, periph->num_parents,periph->flags, NULL, periph->periph); clk_register_clkdev(clk, periph->name, NULL); } //Sync enable count for Ac100 for(i=0; i<ARRAY_SIZE(sunxi_ac100_init); i++) { periph = &sunxi_ac100_init[i]; clk = clk_get(NULL,periph->name); if(!clk || IS_ERR(clk)) continue; if((!clk->prepare_count) && (!clk->enable_count) && clk->ops->is_enabled(clk->hw)) { clk->prepare_count++; clk->enable_count++; parent = clk->parent; while(parent) { parent->enable_count++; parent->prepare_count++; parent = parent->parent; } } clk_put(clk); } return 0; }