void __init tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks) { struct clk *clk; struct clk **dt_clk; int i; for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) { struct pmc_clk_init_data *data; data = pmc_clks + i; dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks); if (!dt_clk) continue; clk = clk_register_mux(NULL, data->mux_name, data->parents, data->num_parents, CLK_SET_RATE_NO_REPARENT, pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift, 3, 0, &clk_out_lock); *dt_clk = clk; dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks); if (!dt_clk) continue; clk = clk_register_gate(NULL, data->gate_name, data->mux_name, 0, pmc_base + PMC_CLK_OUT_CNTRL, data->gate_shift, 0, &clk_out_lock); *dt_clk = clk; clk_register_clkdev(clk, data->dev_name, data->gate_name); } /* blink */ writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, pmc_base + PMC_DPD_PADS_ORIDE, PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks); if (!dt_clk) return; clk = clk_register_gate(NULL, "blink", "blink_override", 0, pmc_base + PMC_CTRL, PMC_CTRL_BLINK_ENB, 0, NULL); clk_register_clkdev(clk, "blink", NULL); *dt_clk = clk; }
static int ti_adpll_init_gate(struct ti_adpll_data *d, enum ti_adpll_clocks index, int output_index, char *name, struct clk *parent_clock, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags) { const char *child_name; const char *parent_name; struct clk *clock; child_name = ti_adpll_clk_get_name(d, output_index, name); if (!child_name) return -EINVAL; parent_name = __clk_get_name(parent_clock); clock = clk_register_gate(d->dev, child_name, parent_name, 0, reg, bit_idx, clk_gate_flags, &d->lock); if (IS_ERR(clock)) { dev_err(d->dev, "failed to register gate %s: %li\n", name, PTR_ERR(clock)); return PTR_ERR(clock); } return ti_adpll_setup_clock(d, clock, index, output_index, child_name, clk_unregister_gate); }
void mmp_register_general_gate_clks(struct mmp_clk_unit *unit, struct mmp_param_general_gate_clk *clks, void __iomem *base, int size) { struct clk *clk; int i; for (i = 0; i < size; i++) { clk = clk_register_gate(NULL, clks[i].name, clks[i].parent_name, clks[i].flags, base + clks[i].offset, clks[i].bit_idx, clks[i].gate_flags, clks[i].lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); continue; } if (clks[i].id) unit->clk_table[clks[i].id] = clk; } }
/* register a list of gate clocks */ void __init amlogic_clk_register_gate(struct amlogic_gate_clock *list, unsigned int nr_clk) { struct clk *clk; unsigned int idx, ret; void __iomem *base; for (idx = 0; idx < nr_clk; idx++, list++) { if (list->is_ao) base = reg_base_ao; /*ao bus*/ else base = reg_base; /* cbus */ clk = clk_register_gate(NULL, list->name, list->parent_name, list->flags, base + list->offset, list->bit_idx, list->gate_flags, &lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, list->name); continue; } /* register a clock lookup only if a clock alias is specified */ if (list->name) { ret = clk_register_clkdev(clk, list->name, list->dev_name); if (ret) pr_err("%s: failed to register lookup %s\n", __func__, list->name); } amlogic_clk_add_lookup(clk, list->id); } }
static struct clk __init *dove_register_gate(const char *name, const char *parent, u8 bit_idx) { return clk_register_gate(NULL, name, parent, 0, (void __iomem *)CLOCK_GATING_CONTROL, bit_idx, 0, &gating_lock); }
int hisi_clk_register_gate(const struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) { struct clk *clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { clk = clk_register_gate(NULL, clks[i].name, clks[i].parent_name, clks[i].flags, base + clks[i].offset, clks[i].bit_idx, clks[i].gate_flags, &hisi_clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); goto err; } if (clks[i].alias) clk_register_clkdev(clk, clks[i].alias, NULL); data->clk_data.clks[clks[i].id] = clk; } return 0; err: while (i--) clk_unregister_gate(data->clk_data.clks[clks[i].id]); return PTR_ERR(clk); }
static void __init mvebu_clk_gating_setup( struct device_node *np, const struct mvebu_soc_descr *descr) { struct mvebu_gating_ctrl *ctrl; struct clk *clk; void __iomem *base; const char *default_parent = NULL; int n; base = of_iomap(np, 0); clk = of_clk_get(np, 0); if (!IS_ERR(clk)) { default_parent = __clk_get_name(clk); clk_put(clk); } ctrl = kzalloc(sizeof(struct mvebu_gating_ctrl), GFP_KERNEL); if (WARN_ON(!ctrl)) return; spin_lock_init(&ctrl->lock); /* * Count, allocate, and register clock gates */ for (n = 0; descr[n].name;) n++; ctrl->num_gates = n; ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), GFP_KERNEL); if (WARN_ON(!ctrl->gates)) { kfree(ctrl); return; } for (n = 0; n < ctrl->num_gates; n++) { u8 flags = 0; const char *parent = (descr[n].parent) ? descr[n].parent : default_parent; /* * On Armada 370, the DDR clock is a special case: it * isn't taken by any driver, but should anyway be * kept enabled, so we mark it as IGNORE_UNUSED for * now. */ if (!strcmp(descr[n].name, "ddr")) flags |= CLK_IGNORE_UNUSED; ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent, flags, base, descr[n].bit_idx, 0, &ctrl->lock); WARN_ON(IS_ERR(ctrl->gates[n])); } of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl); }
static void __init tegra_sclk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { struct clk *clk; struct clk **dt_clk; /* SCLK */ dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks); if (dt_clk) { clk = tegra_clk_register_super_mux("sclk", sclk_parents, ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT, clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); *dt_clk = clk; } /* HCLK */ dt_clk = tegra_lookup_dt_id(tegra_clk_hclk, tegra_clks); if (dt_clk) { clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, clk_base + SYSTEM_CLK_RATE, 4, 2, 0, &sysrate_lock); clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); *dt_clk = clk; } /* PCLK */ dt_clk = tegra_lookup_dt_id(tegra_clk_pclk, tegra_clks); if (!dt_clk) return; clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, clk_base + SYSTEM_CLK_RATE, 0, 2, 0, &sysrate_lock); clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); *dt_clk = clk; }
static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, enum zynq_clk clk1, const char *clk_name0, const char *clk_name1, void __iomem *clk_ctrl, const char **parents, unsigned int two_gates) { struct clk *clk; char *mux_name; char *div_name; spinlock_t *lock; lock = kmalloc(sizeof(*lock), GFP_KERNEL); if (!lock) goto err; spin_lock_init(lock); mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); clk = clk_register_mux(NULL, mux_name, parents, 4, CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); if (two_gates) clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); kfree(mux_name); kfree(div_name); return; err: clks[clk0] = ERR_PTR(-ENOMEM); if (two_gates) clks[clk1] = ERR_PTR(-ENOMEM); }
void __init mvebu_clk_gating_setup(struct device_node *np, const struct clk_gating_soc_desc *desc) { struct clk_gating_ctrl *ctrl; struct clk *clk; void __iomem *base; const char *default_parent = NULL; int n; base = of_iomap(np, 0); if (WARN_ON(!base)) return; clk = of_clk_get(np, 0); if (!IS_ERR(clk)) { default_parent = __clk_get_name(clk); clk_put(clk); } ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); if (WARN_ON(!ctrl)) goto ctrl_out; spin_lock_init(&ctrl->lock); /* Count, allocate, and register clock gates */ for (n = 0; desc[n].name;) n++; ctrl->num_gates = n; ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), GFP_KERNEL); if (WARN_ON(!ctrl->gates)) goto gates_out; for (n = 0; n < ctrl->num_gates; n++) { const char *parent = (desc[n].parent) ? desc[n].parent : default_parent; ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent, desc[n].flags, base, desc[n].bit_idx, 0, &ctrl->lock); WARN_ON(IS_ERR(ctrl->gates[n])); } of_clk_add_provider(np, clk_gating_get_src, ctrl); return; gates_out: kfree(ctrl); ctrl_out: iounmap(base); }
static void __init zynq_clk_register_fclk(enum zynq_clk fclk, const char *clk_name, void __iomem *fclk_ctrl_reg, const char **parents) { struct clk *clk; char *mux_name; char *div0_name; char *div1_name; spinlock_t *fclk_lock; spinlock_t *fclk_gate_lock; void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); if (!fclk_lock) goto err; fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); if (!fclk_gate_lock) goto err; spin_lock_init(fclk_lock); spin_lock_init(fclk_gate_lock); mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); clk = clk_register_mux(NULL, mux_name, parents, 4, 0, fclk_ctrl_reg, 4, 2, 0, fclk_lock); clk = clk_register_divider(NULL, div0_name, mux_name, 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, fclk_lock); clk = clk_register_divider(NULL, div1_name, div0_name, CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, fclk_lock); clks[fclk] = clk_register_gate(NULL, clk_name, div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); kfree(mux_name); kfree(div0_name); kfree(div1_name); return; err: clks[fclk] = ERR_PTR(-ENOMEM); }
void pistachio_clk_register_gate(struct pistachio_clk_provider *p, struct pistachio_gate *gate, unsigned int num) { struct clk *clk; unsigned int i; for (i = 0; i < num; i++) { clk = clk_register_gate(NULL, gate[i].name, gate[i].parent, CLK_SET_RATE_PARENT, p->base + gate[i].reg, gate[i].shift, 0, NULL); p->clk_data.clks[gate[i].id] = clk; } }
static void __init zynq_clk_setup(struct device_node *np) { int i; u32 tmp; int ret; struct clk *clk; char *clk_name; unsigned int fclk_enable = 0; const char *clk_output_name[clk_max]; const char *cpu_parents[4]; const char *periph_parents[4]; const char *swdt_ext_clk_mux_parents[2]; const char *can_mio_mux_parents[NUM_MIO_PINS]; pr_info("Zynq clock init\n"); /* get clock output names from DT */ for (i = 0; i < clk_max; i++) { if (of_property_read_string_index(np, "clock-output-names", i, &clk_output_name[i])) { pr_err("%s: clock output name not in DT\n", __func__); BUG(); } } cpu_parents[0] = clk_output_name[armpll]; cpu_parents[1] = clk_output_name[armpll]; cpu_parents[2] = clk_output_name[ddrpll]; cpu_parents[3] = clk_output_name[iopll]; periph_parents[0] = clk_output_name[iopll]; periph_parents[1] = clk_output_name[iopll]; periph_parents[2] = clk_output_name[armpll]; periph_parents[3] = clk_output_name[ddrpll]; of_property_read_u32(np, "fclk-enable", &fclk_enable); /* ps_clk */ ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); if (ret) { pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); tmp = 33333333; } ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT, tmp); ret = of_property_read_u32(np, "fclk-enable", &fclk_enable); if (ret) fclk_enable = 0xf; /* PLLs */ clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, SLCR_PLL_STATUS, 0, &armpll_lock); clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], armpll_parents, 2, CLK_SET_RATE_NO_REPARENT, SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock); clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, SLCR_PLL_STATUS, 1, &ddrpll_lock); clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT, SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock); clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, SLCR_PLL_STATUS, 2, &iopll_lock); clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], iopll_parents, 2, CLK_SET_RATE_NO_REPARENT, SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); /* CPU clocks */ tmp = readl(SLCR_621_TRUE) & 1; clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock); clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, 1, 2); clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], "cpu_3or2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, 2 + tmp); clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 26, 0, &armclk_lock); clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, 4 + 2 * tmp); clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, 0, &armclk_lock); /* Timers */ swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { int idx = of_property_match_string(np, "clock-names", swdt_ext_clk_input_names[i]); if (idx >= 0) swdt_ext_clk_mux_parents[i + 1] = of_clk_get_parent_name(np, idx); else swdt_ext_clk_mux_parents[i + 1] = dummy_nm; } clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0, &swdtclk_lock); /* DDR clocks */ clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); clk_prepare_enable(clks[ddr2x]); clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); clk_prepare_enable(clks[ddr3x]); clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); clk = clk_register_divider(NULL, "dci_div1", "dci_div0", CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, &dciclk_lock); clk_prepare_enable(clks[dci]); /* Peripheral clocks */ for (i = fclk0; i <= fclk3; i++) { int enable = !!(fclk_enable & BIT(i - fclk0)); zynq_clk_register_fclk(i, clk_output_name[i], SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), periph_parents, enable); } zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, SLCR_LQSPI_CLK_CTRL, periph_parents, 0); zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, SLCR_SMC_CLK_CTRL, periph_parents, 0); zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, SLCR_PCAP_CLK_CTRL, periph_parents, 0); zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, periph_parents, 1); zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], clk_output_name[uart1], SLCR_UART_CLK_CTRL, periph_parents, 1); zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], clk_output_name[spi1], SLCR_SPI_CLK_CTRL, periph_parents, 1); for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { int idx = of_property_match_string(np, "clock-names", gem0_emio_input_names[i]); if (idx >= 0) gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, idx); } clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock); clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0", CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock); clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], "gem0_emio_mux", CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { int idx = of_property_match_string(np, "clock-names", gem1_emio_input_names[i]); if (idx >= 0) gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, idx); } clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock); clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0", CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock); clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], "gem1_emio_mux", CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); tmp = strlen("mio_clk_00x"); clk_name = kmalloc(tmp, GFP_KERNEL); for (i = 0; i < NUM_MIO_PINS; i++) { int idx; snprintf(clk_name, tmp, "mio_clk_%2.2d", i); idx = of_property_match_string(np, "clock-names", clk_name); if (idx >= 0) can_mio_mux_parents[i] = of_clk_get_parent_name(np, idx); else can_mio_mux_parents[i] = dummy_nm; } kfree(clk_name); clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock); clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); clk = clk_register_divider(NULL, "can_div1", "can_div0", CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); clk = clk_register_gate(NULL, "can0_gate", "can_div1", CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, &canclk_lock); clk = clk_register_gate(NULL, "can1_gate", "can_div1", CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, &canclk_lock); clk = clk_register_mux(NULL, "can0_mio_mux", can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock); clk = clk_register_mux(NULL, "can1_mio_mux", can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock); clks[can0] = clk_register_mux(NULL, clk_output_name[can0], can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock); clks[can1] = clk_register_mux(NULL, clk_output_name[can1], can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock); for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { int idx = of_property_match_string(np, "clock-names", dbgtrc_emio_input_names[i]); if (idx >= 0) dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, idx); } clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock); clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock); clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, 0, 0, &dbgclk_lock); clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, &dbgclk_lock); /* leave debug clocks in the state the bootloader set them up to */ tmp = clk_readl(SLCR_DBG_CLK_CTRL); if (tmp & DBG_CLK_CTRL_CLKACT_TRC) if (clk_prepare_enable(clks[dbg_trc])) pr_warn("%s: trace clk enable failed\n", __func__); if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT) if (clk_prepare_enable(clks[dbg_apb])) pr_warn("%s: debug APB clk enable failed\n", __func__); /* One gated clock for all APER clocks. */ clks[dma] = clk_register_gate(NULL, clk_output_name[dma], clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, &aperclk_lock); clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, &aperclk_lock); clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, &aperclk_lock); clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, &aperclk_lock); clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, &aperclk_lock); clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, &aperclk_lock); clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, &aperclk_lock); clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, &aperclk_lock); clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, &aperclk_lock); clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, &aperclk_lock); clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, &aperclk_lock); clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, &aperclk_lock); clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, &aperclk_lock); clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, &aperclk_lock); clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, &aperclk_lock); clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, &aperclk_lock); clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, &aperclk_lock); clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, &aperclk_lock); for (i = 0; i < ARRAY_SIZE(clks); i++) { if (IS_ERR(clks[i])) { pr_err("Zynq clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); BUG(); } } clk_data.clks = clks; clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); }
static void __init mx28_clocks_init(struct device_node *np) { struct device_node *dcnp; u32 i; dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl"); digctrl = of_iomap(dcnp, 0); WARN_ON(!digctrl); of_node_put(dcnp); clkctrl = of_iomap(np, 0); WARN_ON(!clkctrl); clk_misc_init(); clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2); clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0)); clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0)); clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi)); clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0)); clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0)); clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1)); clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1)); clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels)); clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix)); clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels)); clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31); clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29); clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29); clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29); clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29); clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29); clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29); clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27); clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29); clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29); clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16); clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4); clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31); clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31); clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31); clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31); clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31); clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31); clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31); clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31); clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30); clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30); clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28); clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2); clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16); clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock); clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock); clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); for (i = 0; i < ARRAY_SIZE(clks); i++) if (IS_ERR(clks[i])) { pr_err("i.MX28 clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); return; } clk_data.clks = clks; clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); clk_register_clkdev(clks[enet_out], NULL, "enet_out"); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); }
static void __init zynq_clk_register_fclk(enum zynq_clk fclk, const char *clk_name, void __iomem *fclk_ctrl_reg, const char **parents, int enable) { struct clk *clk; u32 enable_reg; char *mux_name; char *div0_name; char *div1_name; spinlock_t *fclk_lock; spinlock_t *fclk_gate_lock; void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); if (!fclk_lock) goto err; fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); if (!fclk_gate_lock) goto err_fclk_gate_lock; spin_lock_init(fclk_lock); spin_lock_init(fclk_gate_lock); mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); if (!mux_name) goto err_mux_name; div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); if (!div0_name) goto err_div0_name; div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); if (!div1_name) goto err_div1_name; clk = clk_register_mux(NULL, mux_name, parents, 4, CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0, fclk_lock); clk = clk_register_divider(NULL, div0_name, mux_name, 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, fclk_lock); clk = clk_register_divider(NULL, div1_name, div0_name, CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, fclk_lock); clks[fclk] = clk_register_gate(NULL, clk_name, div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); enable_reg = readl(fclk_gate_reg) & 1; if (enable && !enable_reg) { if (clk_prepare_enable(clks[fclk])) pr_warn("%s: FCLK%u enable failed\n", __func__, fclk - fclk0); } kfree(mux_name); kfree(div0_name); kfree(div1_name); return; err_div1_name: kfree(div0_name); err_div0_name: kfree(mux_name); err_mux_name: kfree(fclk_gate_lock); err_fclk_gate_lock: kfree(fclk_lock); err: clks[fclk] = ERR_PTR(-ENOMEM); }
int __init mx28_clocks_init(void) { int i; clk_misc_init(); clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2); clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0)); clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0)); clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi)); clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0)); clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0)); clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1)); clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1)); clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels)); clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix)); clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels)); clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31); clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29); clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29); clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29); clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29); clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29); clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29); clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27); clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29); clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29); clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16); clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4); clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31); clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31); clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31); clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31); clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31); clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31); clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31); clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31); clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30); clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30); clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28); clks[usb0] = mxs_clk_gate("usb0", "usb0_pwr", DIGCTRL, 2); clks[usb1] = mxs_clk_gate("usb1", "usb1_pwr", DIGCTRL, 16); clks[usb0_pwr] = clk_register_gate(NULL, "usb0_pwr", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock); clks[usb1_pwr] = clk_register_gate(NULL, "usb1_pwr", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock); clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); for (i = 0; i < ARRAY_SIZE(clks); i++) if (IS_ERR(clks[i])) { pr_err("i.MX28 clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); return PTR_ERR(clks[i]); } clk_register_clkdev(clks[clk32k], NULL, "timrot"); clk_register_clkdev(clks[enet_out], NULL, "enet_out"); clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups)); clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups)); clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups)); clk_register_clkdevs(clks[ssp0], ssp0_lookups, ARRAY_SIZE(ssp0_lookups)); clk_register_clkdevs(clks[ssp1], ssp1_lookups, ARRAY_SIZE(ssp1_lookups)); clk_register_clkdevs(clks[ssp2], ssp2_lookups, ARRAY_SIZE(ssp2_lookups)); clk_register_clkdevs(clks[ssp3], ssp3_lookups, ARRAY_SIZE(ssp3_lookups)); clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups)); clk_register_clkdevs(clks[saif0], saif0_lookups, ARRAY_SIZE(saif0_lookups)); clk_register_clkdevs(clks[saif1], saif1_lookups, ARRAY_SIZE(saif1_lookups)); clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups)); clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups)); clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups)); clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups)); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); mxs_timer_init(MX28_INT_TIMER0); return 0; }
void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) { struct clk *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); clk_register_clkdev(clk, "osc_32k_clk", NULL); clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, 24000000); clk_register_clkdev(clk, "osc_24m_clk", NULL); /* clock derived from 32 KHz osc clk */ clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "fc900000.rtc"); /* clock derived from 24 MHz osc clk */ clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, 48000000); clk_register_clkdev(clk, "pll3_clk", NULL); clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "fc880000.wdt"); clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco1_clk", NULL); clk_register_clkdev(clk1, "pll1_clk", NULL); clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco2_clk", NULL); clk_register_clkdev(clk1, "pll2_clk", NULL); /* clock derived from pll1 clk */ clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", CLK_SET_RATE_PARENT, 1, 1); clk_register_clkdev(clk, "cpu_clk", NULL); clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, HCLK_RATIO_MASK, 0, &_lock); clk_register_clkdev(clk, "ahb_clk", NULL); clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "uart_syn_clk", NULL); clk_register_clkdev(clk1, "uart_syn_gclk", NULL); clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart0_mclk", NULL); clk = clk_register_gate(NULL, "uart0", "uart0_mclk", CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0000000.serial"); clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "firda_syn_clk", NULL); clk_register_clkdev(clk1, "firda_syn_gclk", NULL); clk = clk_register_mux(NULL, "firda_mclk", firda_parents, ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "firda_mclk", NULL); clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "firda"); /* gpt clocks */ clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt0"); clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt1_mclk", NULL); clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt1"); clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt2_mclk", NULL); clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt2"); /* general synths clocks */ clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk", 0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "gen0_syn_clk", NULL); clk_register_clkdev(clk1, "gen0_syn_gclk", NULL); clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk", 0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "gen1_syn_clk", NULL); clk_register_clkdev(clk1, "gen1_syn_gclk", NULL); clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents, ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT, CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gen2_3_par_clk", NULL); clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk", "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "gen2_syn_clk", NULL); clk_register_clkdev(clk1, "gen2_syn_gclk", NULL); clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk", "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "gen3_syn_clk", NULL); clk_register_clkdev(clk1, "gen3_syn_gclk", NULL); /* clock derived from pll3 clk */ clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB, USBH_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e1800000.ehci"); clk_register_clkdev(clk, NULL, "e1900000.ohci"); clk_register_clkdev(clk, NULL, "e2100000.ohci"); clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1, 1); clk_register_clkdev(clk, "usbh.0_clk", NULL); clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1, 1); clk_register_clkdev(clk, "usbh.1_clk", NULL); clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e1100000.usbd"); /* clock derived from ahb clk */ clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, 1); clk_register_clkdev(clk, "ahbmult2_clk", NULL); clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "ddr_clk", NULL); clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, PCLK_RATIO_MASK, 0, &_lock); clk_register_clkdev(clk, "apb_clk", NULL); clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG, AMEM_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "amem_clk", NULL); clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB, C3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "c3_clk"); clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, DMA_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "fc400000.dma"); clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, GMAC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0800000.eth"); clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB, I2C_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0180000.i2c"); clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, JPEG_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "jpeg"); clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, SMI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "fc000000.flash"); /* clock derived from apb clk */ clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, ADC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0080000.adc"); clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB, GPIO_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "fc980000.gpio"); clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, SSP_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0100000.spi"); /* RAS clk enable */ clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB, RAS_AHB_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_ahb_clk", NULL); clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB, RAS_APB_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_apb_clk", NULL); clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0, RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_32k_clk", NULL); clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0, RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_24m_clk", NULL); clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0, RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_pll1_clk", NULL); clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_pll2_clk", NULL); clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_pll3_clk", NULL); clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_syn0_gclk", NULL); clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_syn1_gclk", NULL); clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_syn2_gclk", NULL); clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_syn3_gclk", NULL); if (of_machine_is_compatible("st,spear300")) spear300_clk_init(); else if (of_machine_is_compatible("st,spear310")) spear310_clk_init(); else if (of_machine_is_compatible("st,spear320")) spear320_clk_init(soc_config_base); }
void __init mvebu_clk_gating_setup(struct device_node *np, const struct clk_gating_soc_desc *desc) { struct clk *clk; void __iomem *base; const char *default_parent = NULL; int n; if (ctrl) { pr_err("mvebu-clk-gating: cannot instantiate more than one gatable clock device\n"); return; } base = of_iomap(np, 0); if (WARN_ON(!base)) return; clk = of_clk_get(np, 0); if (!IS_ERR(clk)) { default_parent = __clk_get_name(clk); clk_put(clk); } ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); if (WARN_ON(!ctrl)) goto ctrl_out; /* lock must already be initialized */ ctrl->lock = &ctrl_gating_lock; ctrl->base = base; /* Count, allocate, and register clock gates */ for (n = 0; desc[n].name;) n++; ctrl->num_gates = n; ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), GFP_KERNEL); if (WARN_ON(!ctrl->gates)) goto gates_out; for (n = 0; n < ctrl->num_gates; n++) { const char *parent = (desc[n].parent) ? desc[n].parent : default_parent; ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent, desc[n].flags, base, desc[n].bit_idx, 0, ctrl->lock); WARN_ON(IS_ERR(ctrl->gates[n])); } of_clk_add_provider(np, clk_gating_get_src, ctrl); register_syscore_ops(&clk_gate_syscore_ops); return; gates_out: kfree(ctrl); ctrl_out: iounmap(base); }
static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params) { struct clk *clk; struct clk **dt_clk; int i; dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks); if (dt_clk) { /* PLLP */ clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0, pll_params, NULL); clk_register_clkdev(clk, "pll_p", NULL); *dt_clk = clk; } for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) { struct pll_out_data *data; data = pllp_out_clks + i; dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); if (!dt_clk) continue; clk = tegra_clk_register_divider(data->div_name, "pll_p", clk_base + data->offset, 0, data->div_flags, data->div_shift, 8, 1, data->lock); clk = tegra_clk_register_pll_out(data->pll_out_name, data->div_name, clk_base + data->offset, data->rst_shift + 1, data->rst_shift, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, data->lock); *dt_clk = clk; } dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_cpu, tegra_clks); if (dt_clk) { /* * Tegra210 has control on enabling/disabling PLLP branches to * CPU, register a gate clock "pll_p_out_cpu" for this gating * function and parent "pll_p_out4" to it, so when we are * re-parenting CPU off from "pll_p_out4" the PLLP branching to * CPU can be disabled automatically. */ clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24, 8, 1, &PLLP_OUTB_lock); dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out4_cpu, tegra_clks); if (dt_clk) { clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", clk_base + PLLP_OUTB, 17, 16, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, &PLLP_OUTB_lock); *dt_clk = clk; } } dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_hsio, tegra_clks); if (dt_clk) { /* PLLP_OUT_HSIO */ clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 29, 0, NULL); *dt_clk = clk; } dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_xusb, tegra_clks); if (dt_clk) { /* PLLP_OUT_XUSB */ clk = clk_register_gate(NULL, "pll_p_out_xusb", "pll_p_out_hsio", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0, NULL); clk_register_clkdev(clk, "pll_p_out_xusb", NULL); *dt_clk = clk; } }
static void __init berlin2q_clock_setup(struct device_node *np) { const char *parent_names[9]; struct clk *clk; int n; gbase = of_iomap(np, 0); if (!gbase) { pr_err("%s: Unable to map global base\n", np->full_name); return; } /* BG2Q CPU PLL is not part of global registers */ cpupll_base = of_iomap(np, 1); if (!cpupll_base) { pr_err("%s: Unable to map cpupll base\n", np->full_name); iounmap(gbase); return; } /* overwrite default clock names with DT provided ones */ clk = of_clk_get_by_name(np, clk_names[REFCLK]); if (!IS_ERR(clk)) { clk_names[REFCLK] = __clk_get_name(clk); clk_put(clk); } /* simple register PLLs */ clk = berlin2_pll_register(&bg2q_pll_map, gbase + REG_SYSPLLCTL0, clk_names[SYSPLL], clk_names[REFCLK], 0); if (IS_ERR(clk)) goto bg2q_fail; clk = berlin2_pll_register(&bg2q_pll_map, cpupll_base, clk_names[CPUPLL], clk_names[REFCLK], 0); if (IS_ERR(clk)) goto bg2q_fail; /* TODO: add BG2Q AVPLL */ /* * TODO: add reference clock bypass switches: * memPLLSWBypass, cpuPLLSWBypass, and sysPLLSWBypass */ /* clock divider cells */ for (n = 0; n < ARRAY_SIZE(bg2q_divs); n++) { const struct berlin2_div_data *dd = &bg2q_divs[n]; int k; for (k = 0; k < dd->num_parents; k++) parent_names[k] = clk_names[dd->parent_ids[k]]; clks[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase, dd->name, dd->div_flags, parent_names, dd->num_parents, dd->flags, &lock); } /* clock gate cells */ for (n = 0; n < ARRAY_SIZE(bg2q_gates); n++) { const struct berlin2_gate_data *gd = &bg2q_gates[n]; clks[CLKID_GFX2DAXI + n] = clk_register_gate(NULL, gd->name, gd->parent_name, gd->flags, gbase + REG_CLKENABLE, gd->bit_idx, 0, &lock); } /* * twdclk is derived from cpu/3 * TODO: use cpupll until cpuclk is not available */ clks[CLKID_TWD] = clk_register_fixed_factor(NULL, "twd", clk_names[CPUPLL], 0, 1, 3); /* check for errors on leaf clocks */ for (n = 0; n < MAX_CLKS; n++) { if (!IS_ERR(clks[n])) continue; pr_err("%s: Unable to register leaf clock %d\n", np->full_name, n); goto bg2q_fail; } /* register clk-provider */ clk_data.clks = clks; clk_data.clk_num = MAX_CLKS; of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); return; bg2q_fail: iounmap(cpupll_base); iounmap(gbase); }
void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) { struct clk *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 32000); clk_register_clkdev(clk, "osc_32k_clk", NULL); clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, 24000000); clk_register_clkdev(clk, "osc_24m_clk", NULL); clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, 25000000); clk_register_clkdev(clk, "osc_25m_clk", NULL); clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, 125000000); clk_register_clkdev(clk, "gmii_pad_clk", NULL); clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, CLK_IS_ROOT, 12288000); clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); /* clock derived from 32 KHz osc clk */ clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0580000.rtc"); /* clock derived from 24 or 25 MHz osc clk */ /* vco-pll */ clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "vco1_mclk", NULL); clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco1_clk", NULL); clk_register_clkdev(clk1, "pll1_clk", NULL); clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "vco2_mclk", NULL); clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco2_clk", NULL); clk_register_clkdev(clk1, "pll2_clk", NULL); clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "vco3_mclk", NULL); clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco3_clk", NULL); clk_register_clkdev(clk1, "pll3_clk", NULL); clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl, ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco4_clk", NULL); clk_register_clkdev(clk1, "pll4_clk", NULL); clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, 48000000); clk_register_clkdev(clk, "pll5_clk", NULL); clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, 25000000); clk_register_clkdev(clk, "pll6_clk", NULL); /* vco div n clocks */ clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, 2); clk_register_clkdev(clk, "vco1div2_clk", NULL); clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, 4); clk_register_clkdev(clk, "vco1div4_clk", NULL); clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, 2); clk_register_clkdev(clk, "vco2div2_clk", NULL); clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, 2); clk_register_clkdev(clk, "vco3div2_clk", NULL); /* peripherals */ clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, 128); clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "spear_thermal"); /* clock derived from pll4 clk */ clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, 1); clk_register_clkdev(clk, "ddr_clk", NULL); /* clock derived from pll1 clk */ clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "cpu_clk", NULL); clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, 2); clk_register_clkdev(clk, NULL, "ec800620.wdt"); clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, 2); clk_register_clkdev(clk, NULL, "smp_twd"); clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, 6); clk_register_clkdev(clk, "ahb_clk", NULL); clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1, 12); clk_register_clkdev(clk, "apb_clk", NULL); /* gpt clocks */ clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt0_mclk", NULL); clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt0"); clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt1_mclk", NULL); clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt1"); clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt2_mclk", NULL); clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt2"); clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt3_mclk", NULL); clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt3"); /* others */ clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk", 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "uart_syn_clk", NULL); clk_register_clkdev(clk1, "uart_syn_gclk", NULL); clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart0_mclk", NULL); clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0000000.serial"); clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "sdhci_syn_clk", NULL); clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b3000000.sdhci"); clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "cfxd_syn_clk", NULL); clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b2800000.cf"); clk_register_clkdev(clk, NULL, "arasan_xd"); clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "c3_syn_clk", NULL); clk_register_clkdev(clk1, "c3_syn_gclk", NULL); clk = clk_register_mux(NULL, "c3_mclk", c3_parents, ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "c3_mclk", NULL); clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "c3"); /* gmac */ clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, ARRAY_SIZE(gmac_phy_input_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG, SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT, SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "phy_input_mclk", NULL); clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", 0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "phy_syn_clk", NULL); clk_register_clkdev(clk1, "phy_syn_gclk", NULL); clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "stmmacphy.0", NULL); /* clcd */ clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, ARRAY_SIZE(clcd_synth_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT, SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "clcd_syn_mclk", NULL); clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl, ARRAY_SIZE(clcd_rtbl), &_lock); clk_register_clkdev(clk, "clcd_syn_clk", NULL); clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, SPEAR1310_CLCD_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e1000000.clcd"); /* i2s */ clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2s_src_mclk", NULL); clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); clk_register_clkdev(clk, "i2s_prs1_clk", NULL); clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock); clk_register_clkdev(clk, "i2s_ref_mclk", NULL); clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG, &i2s_sclk_masks, i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "i2s_sclk_clk", NULL); clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL); /* clock derived from ahb clk */ clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0280000.i2c"); clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "ea800000.dma"); clk_register_clkdev(clk, NULL, "eb000000.dma"); clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b2000000.jpeg"); clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e2000000.eth"); clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b0000000.flash"); clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "ea000000.flash"); clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e4000000.ohci"); clk_register_clkdev(clk, NULL, "e4800000.ehci"); clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e5000000.ohci"); clk_register_clkdev(clk, NULL, "e5800000.ehci"); clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e3800000.otg"); clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b1000000.pcie"); clk_register_clkdev(clk, NULL, "b1000000.ahci"); clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b1800000.pcie"); clk_register_clkdev(clk, NULL, "b1800000.ahci"); clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b4000000.pcie"); clk_register_clkdev(clk, NULL, "b4000000.ahci"); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "sysram0_clk", NULL); clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "sysram1_clk", NULL); clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl, ARRAY_SIZE(adc_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "adc_syn_clk", NULL); clk_register_clkdev(clk1, "adc_syn_gclk", NULL); clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0080000.adc"); /* clock derived from apb clk */ clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0100000.spi"); clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0600000.gpio"); clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0680000.gpio"); clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0180000.i2s"); clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0200000.i2s"); clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0300000.kbd"); /* RAS clks */ clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT0_1_CLK_SHIFT, SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT2_3_CLK_SHIFT, SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0, SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn0_clk", NULL); clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0, SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn1_clk", NULL); clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0, SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn2_clk", NULL); clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0, SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn3_clk", NULL); clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_osc_24m_clk", NULL); clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_osc_25m_clk", NULL); clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_osc_32k_clk", NULL); clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_pll2_clk", NULL); clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_pll3_clk", NULL); clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_tx125_clk", NULL); clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0, 30000000); clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_30m_clk", NULL); clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0, 48000000); clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_48m_clk", NULL); clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_ahb_clk", NULL); clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_apb_clk", NULL); clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT, 50000000); clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT, 50000000); clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "c_can_platform.0"); clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "c_can_platform.1"); clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c400000.eth"); clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c500000.eth"); clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c600000.eth"); clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c700000.eth"); clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk", smii_rgmii_phy_parents, ARRAY_SIZE(smii_rgmii_phy_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1, SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT, SPEAR1310_PHY_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "stmmacphy.1", NULL); clk_register_clkdev(clk, "stmmacphy.2", NULL); clk_register_clkdev(clk, "stmmacphy.4", NULL); clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, SPEAR1310_PHY_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "stmmacphy.3", NULL); clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart1_mclk", NULL); clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c800000.serial"); clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart2_mclk", NULL); clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c900000.serial"); clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart3_mclk", NULL); clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5ca00000.serial"); clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart4_mclk", NULL); clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5cb00000.serial"); clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart5_mclk", NULL); clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5cc00000.serial"); clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c1_mclk", NULL); clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5cd00000.i2c"); clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c2_mclk", NULL); clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5ce00000.i2c"); clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c3_mclk", NULL); clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5cf00000.i2c"); clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c4_mclk", NULL); clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5d000000.i2c"); clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c5_mclk", NULL); clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5d100000.i2c"); clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c6_mclk", NULL); clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5d200000.i2c"); clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c7_mclk", NULL); clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5d300000.i2c"); clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents, ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "ssp1_mclk", NULL); clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5d400000.spi"); clk = clk_register_mux(NULL, "pci_mclk", pci_parents, ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "pci_mclk", NULL); clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "pci"); clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents, ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "tdm1_mclk", NULL); clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents, ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "tdm2_mclk", NULL); clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); }
static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct clk_onecell_data *clk_data; const char *clk_parent; const char *clk_name; struct resource *r; void __iomem *reg; int gate_id; int ngates; int i; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg = devm_ioremap_resource(&pdev->dev, r); if (IS_ERR(reg)) return PTR_ERR(reg); clk_parent = of_clk_get_parent_name(np, 0); if (!clk_parent) return -EINVAL; ngates = of_property_count_strings(np, "clock-output-names"); if (ngates < 0) return ngates; if (!ngates || ngates > SUN6I_APB0_GATES_MAX_SIZE) return -EINVAL; clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data), GFP_KERNEL); if (!clk_data) return -ENOMEM; clk_data->clks = devm_kzalloc(&pdev->dev, SUN6I_APB0_GATES_MAX_SIZE * sizeof(struct clk *), GFP_KERNEL); if (!clk_data->clks) return -ENOMEM; for (i = 0; i < ngates; i++) { of_property_read_string_index(np, "clock-output-names", i, &clk_name); gate_id = i; of_property_read_u32_index(np, "clock-indices", i, &gate_id); WARN_ON(gate_id >= SUN6I_APB0_GATES_MAX_SIZE); if (gate_id >= SUN6I_APB0_GATES_MAX_SIZE) continue; clk_data->clks[gate_id] = clk_register_gate(&pdev->dev, clk_name, clk_parent, 0, reg, gate_id, 0, NULL); WARN_ON(IS_ERR(clk_data->clks[gate_id])); } clk_data->clk_num = ngates; return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); }
void __init rockchip_clk_register_branches( struct rockchip_clk_branch *list, unsigned int nr_clk) { struct clk *clk = NULL; unsigned int idx; unsigned long flags; for (idx = 0; idx < nr_clk; idx++, list++) { flags = list->flags; /* catch simple muxes */ switch (list->branch_type) { case branch_mux: clk = clk_register_mux(NULL, list->name, list->parent_names, list->num_parents, flags, reg_base + list->muxdiv_offset, list->mux_shift, list->mux_width, list->mux_flags, &clk_lock); break; case branch_divider: if (list->div_table) clk = clk_register_divider_table(NULL, list->name, list->parent_names[0], flags, reg_base + list->muxdiv_offset, list->div_shift, list->div_width, list->div_flags, list->div_table, &clk_lock); else clk = clk_register_divider(NULL, list->name, list->parent_names[0], flags, reg_base + list->muxdiv_offset, list->div_shift, list->div_width, list->div_flags, &clk_lock); break; case branch_fraction_divider: clk = rockchip_clk_register_frac_branch(list->name, list->parent_names, list->num_parents, reg_base, list->muxdiv_offset, list->div_flags, list->gate_offset, list->gate_shift, list->gate_flags, flags, list->child, &clk_lock); break; case branch_gate: flags |= CLK_SET_RATE_PARENT; clk = clk_register_gate(NULL, list->name, list->parent_names[0], flags, reg_base + list->gate_offset, list->gate_shift, list->gate_flags, &clk_lock); break; case branch_composite: clk = rockchip_clk_register_branch(list->name, list->parent_names, list->num_parents, reg_base, list->muxdiv_offset, list->mux_shift, list->mux_width, list->mux_flags, list->div_shift, list->div_width, list->div_flags, list->div_table, list->gate_offset, list->gate_shift, list->gate_flags, flags, &clk_lock); break; case branch_mmc: clk = rockchip_clk_register_mmc( list->name, list->parent_names, list->num_parents, reg_base + list->muxdiv_offset, list->div_shift ); break; case branch_inverter: clk = rockchip_clk_register_inverter( list->name, list->parent_names, list->num_parents, reg_base + list->muxdiv_offset, list->div_shift, list->div_flags, &clk_lock); break; case branch_factor: clk = rockchip_clk_register_factor_branch( list->name, list->parent_names, list->num_parents, reg_base, list->div_shift, list->div_width, list->gate_offset, list->gate_shift, list->gate_flags, flags, &clk_lock); break; } /* none of the cases above matched */ if (!clk) { pr_err("%s: unknown clock type %d\n", __func__, list->branch_type); continue; } if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s: %ld\n", __func__, list->name, PTR_ERR(clk)); continue; } rockchip_clk_add_lookup(clk, list->id); } }
int __init mx23_clocks_init(void) { int i; clk_misc_init(); clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io)); clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels)); clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29); clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29); clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29); clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29); clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29); clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16); clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4); clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28); clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30); clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31); clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31); clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31); clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31); clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); clks[usb] = mxs_clk_gate("usb", "usb_pwr", DIGCTRL, 2); clks[usb_pwr] = clk_register_gate(NULL, "usb_pwr", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock); for (i = 0; i < ARRAY_SIZE(clks); i++) if (IS_ERR(clks[i])) { pr_err("i.MX23 clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); return PTR_ERR(clks[i]); } clk_register_clkdev(clks[clk32k], NULL, "timrot"); clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups)); clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups)); clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups)); clk_register_clkdevs(clks[ssp], ssp_lookups, ARRAY_SIZE(ssp_lookups)); clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups)); clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups)); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); mxs_timer_init(MX23_INT_TIMER0); return 0; }
void __init spear6xx_clk_init(void __iomem *misc_base) { struct clk *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); clk_register_clkdev(clk, "osc_32k_clk", NULL); clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000); clk_register_clkdev(clk, "osc_30m_clk", NULL); /* clock derived from 32 KHz osc clk */ clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "rtc-spear"); /* clock derived from 30 MHz osc clk */ clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, 48000000); clk_register_clkdev(clk, "pll3_clk", NULL); clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco1_clk", NULL); clk_register_clkdev(clk1, "pll1_clk", NULL); clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco2_clk", NULL); clk_register_clkdev(clk1, "pll2_clk", NULL); clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "wdt"); /* clock derived from pll1 clk */ clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", CLK_SET_RATE_PARENT, 1, 1); clk_register_clkdev(clk, "cpu_clk", NULL); clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, HCLK_RATIO_MASK, 0, &_lock); clk_register_clkdev(clk, "ahb_clk", NULL); clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "uart_syn_clk", NULL); clk_register_clkdev(clk1, "uart_syn_gclk", NULL); clk = clk_register_mux(NULL, "uart_mclk", uart_parents, ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart_mclk", NULL); clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB, UART0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0000000.serial"); clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB, UART1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0080000.serial"); clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "firda_syn_clk", NULL); clk_register_clkdev(clk1, "firda_syn_gclk", NULL); clk = clk_register_mux(NULL, "firda_mclk", firda_parents, ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "firda_mclk", NULL); clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "firda"); clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk", 0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "clcd_syn_clk", NULL); clk_register_clkdev(clk1, "clcd_syn_gclk", NULL); clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents, ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "clcd_mclk", NULL); clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0, PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "clcd"); /* gpt clocks */ clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL); clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents, ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt0"); clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents, ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt1_mclk", NULL); clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt1"); clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); clk_register_clkdev(clk, "gpt2_syn_clk", NULL); clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt2_mclk", NULL); clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt2"); clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); clk_register_clkdev(clk, "gpt3_syn_clk", NULL); clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents, ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt3_mclk", NULL); clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt3"); /* clock derived from pll3 clk */ clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0, PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e1800000.ehci"); clk_register_clkdev(clk, NULL, "e1900000.ohci"); clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0, PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e2000000.ehci"); clk_register_clkdev(clk, NULL, "e2100000.ohci"); clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "designware_udc"); /* clock derived from ahb clk */ clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, 1); clk_register_clkdev(clk, "ahbmult2_clk", NULL); clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "ddr_clk", NULL); clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, PCLK_RATIO_MASK, 0, &_lock); clk_register_clkdev(clk, "apb_clk", NULL); clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, DMA_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "fc400000.dma"); clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB, FSMC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d1800000.flash"); clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, GMAC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0800000.ethernet"); clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB, I2C_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0200000.i2c"); clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, JPEG_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "jpeg"); clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, SMI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "fc000000.flash"); /* clock derived from apb clk */ clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, ADC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d820b000.adc"); clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "f0100000.gpio"); clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB, GPIO1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "fc980000.gpio"); clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB, GPIO2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d8100000.gpio"); clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, SSP0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "ssp-pl022.0"); clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB, SSP1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "ssp-pl022.1"); clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB, SSP2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "ssp-pl022.2"); }
void __init spear1340_clk_init(void __iomem *misc_base) { struct clk *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); clk_register_clkdev(clk, "osc_32k_clk", NULL); clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); clk_register_clkdev(clk, "osc_24m_clk", NULL); clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); clk_register_clkdev(clk, "osc_25m_clk", NULL); clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); clk_register_clkdev(clk, "gmii_pad_clk", NULL); clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, 12288000); clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); /* clock derived from 32 KHz osc clk */ clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0580000.rtc"); /* clock derived from 24 or 25 MHz osc clk */ /* vco-pll */ clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG, SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "vco1_mclk", NULL); clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0, SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco1_clk", NULL); clk_register_clkdev(clk1, "pll1_clk", NULL); clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG, SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "vco2_mclk", NULL); clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0, SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco2_clk", NULL); clk_register_clkdev(clk1, "pll2_clk", NULL); clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG, SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "vco3_mclk", NULL); clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0, SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco3_clk", NULL); clk_register_clkdev(clk1, "pll3_clk", NULL); clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", 0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl, ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco4_clk", NULL); clk_register_clkdev(clk1, "pll4_clk", NULL); clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, 48000000); clk_register_clkdev(clk, "pll5_clk", NULL); clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, 25000000); clk_register_clkdev(clk, "pll6_clk", NULL); /* vco div n clocks */ clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, 2); clk_register_clkdev(clk, "vco1div2_clk", NULL); clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, 4); clk_register_clkdev(clk, "vco1div4_clk", NULL); clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, 2); clk_register_clkdev(clk, "vco2div2_clk", NULL); clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, 2); clk_register_clkdev(clk, "vco3div2_clk", NULL); /* peripherals */ clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, 128); clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e07008c4.thermal"); /* clock derived from pll4 clk */ clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, 1); clk_register_clkdev(clk, "ddr_clk", NULL); /* clock derived from pll1 clk */ clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0, SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl, ARRAY_SIZE(sys_synth_rtbl), &_lock); clk_register_clkdev(clk, "sys_syn_clk", NULL); clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0, SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl, ARRAY_SIZE(amba_synth_rtbl), &_lock); clk_register_clkdev(clk, "amba_syn_clk", NULL); clk = clk_register_mux(NULL, "sys_mclk", sys_parents, ARRAY_SIZE(sys_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_SYS_CLK_CTRL, SPEAR1340_SCLK_SRC_SEL_SHIFT, SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock); clk_register_clkdev(clk, "sys_mclk", NULL); clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1, 2); clk_register_clkdev(clk, "cpu_clk", NULL); clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1, 3); clk_register_clkdev(clk, "cpu_div3_clk", NULL); clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, 2); clk_register_clkdev(clk, NULL, "ec800620.wdt"); clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, 2); clk_register_clkdev(clk, NULL, "smp_twd"); clk = clk_register_mux(NULL, "ahb_clk", ahb_parents, ARRAY_SIZE(ahb_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_SYS_CLK_CTRL, SPEAR1340_HCLK_SRC_SEL_SHIFT, SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock); clk_register_clkdev(clk, "ahb_clk", NULL); clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2); clk_register_clkdev(clk, "apb_clk", NULL); /* gpt clocks */ clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt0_mclk", NULL); clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt0"); clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt1_mclk", NULL); clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt1"); clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt2_mclk", NULL); clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt2"); clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt3_mclk", NULL); clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt3"); /* others */ clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk", "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "uart0_syn_clk", NULL); clk_register_clkdev(clk1, "uart0_syn_gclk", NULL); clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart0_mclk", NULL); clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0000000.serial"); clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk", "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "uart1_syn_clk", NULL); clk_register_clkdev(clk1, "uart1_syn_gclk", NULL); clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents, ARRAY_SIZE(uart1_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart1_mclk", NULL); clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b4100000.serial"); clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "sdhci_syn_clk", NULL); clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b3000000.sdhci"); clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", 0, SPEAR1340_CFXD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "cfxd_syn_clk", NULL); clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b2800000.cf"); clk_register_clkdev(clk, NULL, "arasan_xd"); clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0, SPEAR1340_C3_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "c3_syn_clk", NULL); clk_register_clkdev(clk1, "c3_syn_gclk", NULL); clk = clk_register_mux(NULL, "c3_mclk", c3_parents, ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "c3_mclk", NULL); clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e1800000.c3"); /* gmac */ clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, ARRAY_SIZE(gmac_phy_input_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_GMAC_CLK_CFG, SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT, SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "phy_input_mclk", NULL); clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", 0, SPEAR1340_GMAC_CLK_SYNT, NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "phy_syn_clk", NULL); clk_register_clkdev(clk1, "phy_syn_gclk", NULL); clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT, SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "stmmacphy.0", NULL); /* clcd */ clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, ARRAY_SIZE(clcd_synth_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT, SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "clcd_syn_mclk", NULL); clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl, ARRAY_SIZE(clcd_rtbl), &_lock); clk_register_clkdev(clk, "clcd_syn_clk", NULL); clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT, SPEAR1340_CLCD_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e1000000.clcd"); /* i2s */ clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2s_src_mclk", NULL); clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); clk_register_clkdev(clk, "i2s_prs1_clk", NULL); clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock); clk_register_clkdev(clk, "i2s_ref_mclk", NULL); clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk", 0, SPEAR1340_I2S_CLK_CFG, &i2s_sclk_masks, i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "i2s_sclk_clk", NULL); clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL); /* clock derived from ahb clk */ clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0280000.i2c"); clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b4000000.i2c"); clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "ea800000.dma"); clk_register_clkdev(clk, NULL, "eb000000.dma"); clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e2000000.eth"); clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b0000000.flash"); clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "ea000000.flash"); clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e4000000.ohci"); clk_register_clkdev(clk, NULL, "e4800000.ehci"); clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e5000000.ohci"); clk_register_clkdev(clk, NULL, "e5800000.ehci"); clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e3800000.otg"); clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b1000000.pcie"); clk_register_clkdev(clk, NULL, "b1000000.ahci"); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "sysram0_clk", NULL); clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "sysram1_clk", NULL); clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl, ARRAY_SIZE(adc_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "adc_syn_clk", NULL); clk_register_clkdev(clk1, "adc_syn_gclk", NULL); clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0080000.adc"); /* clock derived from apb clk */ clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0100000.spi"); clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0600000.gpio"); clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0680000.gpio"); clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b2400000.i2s-play"); clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0, SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b2000000.i2s-rec"); clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0300000.kbd"); /* RAS clks */ clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT0_1_CLK_SHIFT, SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL); clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT2_3_CLK_SHIFT, SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL); clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0, SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn0_clk", NULL); clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0, SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn1_clk", NULL); clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0, SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn2_clk", NULL); clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0, SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn3_clk", NULL); clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk", CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "mali"); clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "spear_cec.0"); clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "spear_cec.1"); clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents, ARRAY_SIZE(spdif_out_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT, SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "spdif_out_mclk", NULL); clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk", CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0000000.spdif-out"); clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents, ARRAY_SIZE(spdif_in_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT, SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "spdif_in_mclk", NULL); clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk", CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0100000.spdif-in"); clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0, SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "acp_clk"); clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e2800000.gpio"); clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "video_dec"); clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "video_enc"); clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "spear_vip"); clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0200000.cam0"); clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0300000.cam1"); clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0400000.cam2"); clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0500000.cam3"); clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0180000.pwm"); }
/* register exynos_audss clocks */ static void __init exynos_audss_clk_init(struct device_node *np) { reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("%s: failed to map audss registers\n", __func__); return; } clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, GFP_KERNEL); if (!clk_table) { pr_err("%s: could not allocate clk lookup table\n", __func__); return; } clk_data.clks = clk_table; clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp", "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL, "dout_aud_bus", "dout_srp", 0, reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s", "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0, &lock); clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk", "dout_srp", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 0, 0, &lock); clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus", "dout_aud_bus", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 2, 0, &lock); clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s", "dout_i2s", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 3, 0, &lock); clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus", "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", "div_pcm0", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); #ifdef CONFIG_PM_SLEEP register_syscore_ops(&exynos_audss_clk_syscore_ops); #endif pr_info("Exynos: Audss: clock setup completed\n"); }
static void __init mx23_clocks_init(struct device_node *np) { struct device_node *dcnp; u32 i; dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl"); digctrl = of_iomap(dcnp, 0); WARN_ON(!digctrl); of_node_put(dcnp); clkctrl = of_iomap(np, 0); WARN_ON(!clkctrl); clk_misc_init(); clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io)); clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels)); clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29); clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29); clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29); clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29); clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29); clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16); clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4); clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28); clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30); clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31); clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31); clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31); clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31); clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2); clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock); for (i = 0; i < ARRAY_SIZE(clks); i++) if (IS_ERR(clks[i])) { pr_err("i.MX23 clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); return; } clk_data.clks = clks; clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); }
static void __init zynq_periph_clk_setup(struct device_node *np) { struct zynq_periph_clk *periph; const char *parent_names[3]; struct clk_init_data init; int clk_num = 0, err; const char *name; struct clk *clk; u32 reg; int i; err = of_property_read_u32(np, "reg", ®); if (WARN_ON(err)) return; periph = kzalloc(sizeof(*periph), GFP_KERNEL); if (WARN_ON(!periph)) return; periph->clk_ctrl = slcr_base + reg; spin_lock_init(&periph->clkact_lock); init.name = np->name; init.ops = &zynq_periph_clk_ops; for (i = 0; i < ARRAY_SIZE(parent_names); i++) parent_names[i] = of_clk_get_parent_name(np, i); init.parent_names = parent_names; init.num_parents = ARRAY_SIZE(parent_names); periph->hw.init = &init; clk = clk_register(NULL, &periph->hw); if (WARN_ON(IS_ERR(clk))) return; err = of_clk_add_provider(np, of_clk_src_simple_get, clk); if (WARN_ON(err)) return; err = of_property_read_string_index(np, "clock-output-names", 0, &name); if (WARN_ON(err)) return; periph->gates[0] = clk_register_gate(NULL, name, np->name, 0, periph->clk_ctrl, 0, 0, &periph->clkact_lock); if (WARN_ON(IS_ERR(periph->gates[0]))) return; clk_num++; /* some periph clks have 2 downstream gates */ err = of_property_read_string_index(np, "clock-output-names", 1, &name); if (err != -ENODATA) { periph->gates[1] = clk_register_gate(NULL, name, np->name, 0, periph->clk_ctrl, 1, 0, &periph->clkact_lock); if (WARN_ON(IS_ERR(periph->gates[1]))) return; clk_num++; } periph->onecell_data.clks = periph->gates; periph->onecell_data.clk_num = clk_num; err = of_clk_add_provider(np, of_clk_src_onecell_get, &periph->onecell_data); if (WARN_ON(err)) return; }
/* register exynos_audss clocks */ static int exynos_audss_clk_probe(struct platform_device *pdev) { int i, ret = 0; struct resource *res; const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; const char *sclk_pcm_p = "sclk_pcm0"; struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; const struct of_device_id *match; enum exynos_audss_clk_type variant; match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node); if (!match) return -EINVAL; variant = (enum exynos_audss_clk_type)match->data; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(reg_base)) { dev_err(&pdev->dev, "failed to map audss registers\n"); return PTR_ERR(reg_base); } clk_table = devm_kzalloc(&pdev->dev, sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, GFP_KERNEL); if (!clk_table) return -ENOMEM; clk_data.clks = clk_table; if (variant == TYPE_EXYNOS5420) clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; else clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1; pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); pll_in = devm_clk_get(&pdev->dev, "pll_in"); if (!IS_ERR(pll_ref)) mout_audss_p[0] = __clk_get_name(pll_ref); if (!IS_ERR(pll_in)) mout_audss_p[1] = __clk_get_name(pll_in); clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); cdclk = devm_clk_get(&pdev->dev, "cdclk"); sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio"); if (!IS_ERR(cdclk)) mout_i2s_p[1] = __clk_get_name(cdclk); if (!IS_ERR(sclk_audio)) mout_i2s_p[2] = __clk_get_name(sclk_audio); clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp", "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL, "dout_aud_bus", "dout_srp", 0, reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s", "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0, &lock); clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk", "dout_srp", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 0, 0, &lock); clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus", "dout_aud_bus", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 2, 0, &lock); clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s", "dout_i2s", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 3, 0, &lock); clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus", "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); if (!IS_ERR(sclk_pcm_in)) sclk_pcm_p = __clk_get_name(sclk_pcm_in); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); if (variant == TYPE_EXYNOS5420) { clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma", "dout_srp", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 9, 0, &lock); } for (i = 0; i < clk_data.clk_num; i++) { if (IS_ERR(clk_table[i])) { dev_err(&pdev->dev, "failed to register clock %d\n", i); ret = PTR_ERR(clk_table[i]); goto unregister; } } ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, &clk_data); if (ret) { dev_err(&pdev->dev, "failed to add clock provider\n"); goto unregister; } #ifdef CONFIG_PM_SLEEP register_syscore_ops(&exynos_audss_clk_syscore_ops); #endif dev_info(&pdev->dev, "setup completed\n"); return 0; unregister: for (i = 0; i < clk_data.clk_num; i++) { if (!IS_ERR(clk_table[i])) clk_unregister(clk_table[i]); } return ret; }