void InitMcbspa(void)
{
// Reset the McBSP
// Disable all interrupts
// Frame sync generator reset
// Sample rate generator reset
// Transmitter reset
// Receiver reset
McbspaRegs.SPCR2.bit.FRST = 0;
McbspaRegs.SPCR2.bit.GRST = 0;
McbspaRegs.SPCR2.bit.XRST = 0;
McbspaRegs.SPCR1.bit.RRST = 0;
// Enable loop back mode
// This does not require external hardware
McbspaRegs.SPCR2.all = 0x0000;
McbspaRegs.SPCR1.all = 0x8000;
// RX data delay is 1 bit
// TX data delay is 1 bit
McbspaRegs.RCR2.bit.RDATDLY = 1;
McbspaRegs.XCR2.bit.XDATDLY = 1;
// No clock sync for CLKG
// Frame-synchronization period
McbspaRegs.SRGR2.bit.GSYNC = 0;
McbspaRegs.SRGR2.bit.FPER = 320;
// Frame-synchronization pulses from
// the sample rate generator
McbspaRegs.SRGR2.bit.FSGM = 1;
// Sample rate generator input clock is LSPCLK
McbspaRegs.SRGR2.bit.CLKSM = 1;
McbspaRegs.PCR.bit.SCLKME = 0;
// Divide-down value for CLKG
// Frame-synchronization pulse width
McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;
clkg_delay_loop();
McbspaRegs.SRGR1.bit.FWID = 1;
// CLKX is driven by the sample rate generator
// Transmit frame synchronization generated by internal
// sample rate generator
McbspaRegs.PCR.bit.CLKXM = 1;
McbspaRegs.PCR.bit.FSXM = 1;
// Enable Sample rate generator and
// wait at least 2 CLKG clock cycles
McbspaRegs.SPCR2.bit.GRST = 1;
clkg_delay_loop();
// Release from reset
// RX, TX and frame sync generator
McbspaRegs.SPCR2.bit.XRST = 1;
McbspaRegs.SPCR1.bit.RRST = 1;
McbspaRegs.SPCR2.bit.FRST = 1;
}
void InitMcbspb(void)
{
// McBSP-B register settings
McbspbRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspbRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
McbspbRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode.
McbspbRegs.MFFINT.all=0x0; // Disable all interrupts
McbspbRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive)
McbspbRegs.RCR1.all=0x0;
McbspbRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit)
McbspbRegs.XCR1.all=0x0;
McbspbRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
McbspbRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods
McbspbRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1)
McbspbRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source
McbspbRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source
delay_loop(); // Wait at least 2 SRG clock cycles
McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
clkg_delay_loop(); // Wait at least 2 CLKG cycles
McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
}
