/*********************************************************************** * * Function: i2s_close * * Purpose: Close the I2S * * Processing: * If init is not TRUE, then return _ERROR to the caller as the * device was not previously opened. Otherwise, disable the I2S * interface and controller and return * _NO_ERROR to the caller. * * Parameters: * devid: Pointer to I2S config structure * * Outputs: None * * Returns: The status of the close operation * * Notes: None * **********************************************************************/ STATUS i2s_close(INT_32 devid) { I2S_CFG_T *pi2s = (I2S_CFG_T *) devid; STATUS status = _ERROR; UNS_32 tmp; /* Close and disable device if it was previously initialized */ if (pi2s->init == TRUE) { /* Place I2S in a default state */ pi2s->regptr->i2s_dao = I2S_MUTE | I2S_STOP | I2S_RESET; pi2s->regptr->i2s_dai = I2S_STOP | I2S_RESET; /* reset Tx rate to default */ pi2s->regptr->i2s_tx_rate = 0; /* reset Rx rate to default */ pi2s->regptr->i2s_rx_rate = 0; /* clear the DMA */ pi2s->regptr->i2s_dma0 = 0; /* clear the DMA */ pi2s->regptr->i2s_dma1 = 0; /* Disable interrupts */ pi2s->regptr->i2s_irq = 0; /* Free I2S and Disable clock */ pi2s->init = FALSE; if (pi2s->i2snum == 0) { clkpwr_clk_en_dis(CLKPWR_I2S0_CLK, 0); } else { clkpwr_clk_en_dis(CLKPWR_I2S1_CLK, 0); } /* relaese the pins muxing */ i2s_pin_mux(pi2s->i2snum, 0); /* return the I2S1 DMA to default */ if (pi2s->i2snum == I2S_CH1) { tmp = CLKPWR->clkpwr_i2s_clk_ctrl; tmp = tmp & ~CLKPWR_I2SCTRL_I2S1_USE_DMA; CLKPWR->clkpwr_i2s_clk_ctrl = tmp; } status = _NO_ERROR; } return status; }
/*********************************************************************** * * Function: ssp_close * * Purpose: Close the SSP * * Processing: * Disable the SSP clock and device. * * Parameters: * devid: Pointer to SSP config structure * * Outputs: None * * Returns: The status of the close operation * * Notes: None * **********************************************************************/ STATUS ssp_close(INT_32 devid) { SSP_DRVDAT_T *sspdrvdat = (SSP_DRVDAT_T *) devid; STATUS status = _ERROR; if (sspdrvdat->init == TRUE) { /* 'Uninitialize' device */ sspdrvdat->init = FALSE; status = _NO_ERROR; /* Disable device */ sspdrvdat->regptr->cr1 &= ~SSP_CR1_SSP_ENABLE; /* Disable clock */ clkpwr_clk_en_dis(sspclks[sspdrvdat->thisdev], 0); } return status; }
/********************************************************************** * * Function: c_entry * * Purpose: Application entry point from the startup code * * Processing: * See function. * * Parameters: None * * Outputs: None * * Returns: Nothing * * Notes: None * *********************************************************************/ void c_entry(void) { SWIM_WINDOW_T win1; COLOR_T clr, *fblog; int idx; INT_32 lcddev; UNS_16 xgs, ygs, curx, cury, curym, xidx; /* Disable interrupts in ARM core */ disable_irq_fiq(); /* Set virtual address of MMU table */ cp15_set_vmmu_addr((void *) (IRAM_BASE + (256 * 1024) - (16 * 1024))); /* Setup miscellaneous board functions */ phy3250_board_init(); /* Setup LCD muxing for STN Color 16BPP */ clkpwr_setup_lcd(CLKPWR_LCDMUX_TFT16, 1); /* Enable clock to LCD block (HCLK_EN)*/ clkpwr_clk_en_dis(CLKPWR_LCD_CLK, 1); /* Setup LCD paramaters in the LCD controller */ lcddev = lcd_open(CLCDC, (INT_32) &LCD_DISPLAY); /* Upper Panel Frame Base Address register */ lcd_ioctl(lcddev, LCD_SET_UP_FB, PHY_LCD_FRAME_BUF); /* Enable LCD controller and power signals */ lcd_ioctl(lcddev, LCD_PWENABLE, 1); /* Enable LCD backlight */ phy3250_lcd_backlight_enable(TRUE); /* Enable LCD power */ phy3250_lcd_power_enable(TRUE); /* Set frame buffer address */ fblog = (COLOR_T *) cp15_map_physical_to_virtual(PHY_LCD_FRAME_BUF); /* Create a SWIM window */ swim_window_open(&win1, LCD_DISPLAY.pixels_per_line, LCD_DISPLAY.lines_per_panel, fblog, 0, 0, (LCD_DISPLAY.pixels_per_line - 1), (LCD_DISPLAY.lines_per_panel - 1),1, WHITE, BLACK, BLACK); /* Compute vertical size for bars */ ygs = LCD_DISPLAY.lines_per_panel / 3; /* Draw Red bars */ cury = 0; curx = 0; curym = ygs - 1; xgs = LCD_DISPLAY.pixels_per_line / RED_COLORS; clr = BLACK; for (xidx = 0; xidx < RED_COLORS; xidx++) { swim_set_pen_color(&win1, clr); for (idx = 0; idx <= xgs; idx++) { swim_put_line(&win1, curx, cury, curx, curym); curx++; } clr = clr + 0x0800; } /* Draw green bars */ cury = cury + ygs; curx = 0; curym = cury + (ygs - 1); xgs = LCD_DISPLAY.pixels_per_line / GREEN_COLORS; clr = BLACK; for (xidx = 0; xidx < GREEN_COLORS; xidx++) { swim_set_pen_color(&win1, clr); for (idx = 0; idx <= xgs; idx++) { swim_put_line(&win1, curx, cury, curx, curym); curx++; } clr = clr + 0x0020; } /* Draw blue bars */ cury = cury + ygs; curx = 0; curym = cury + (ygs - 1); xgs = LCD_DISPLAY.pixels_per_line / BLUE_COLORS; clr = BLACK; for (xidx = 0; xidx < BLUE_COLORS; xidx++) { swim_set_pen_color(&win1, clr); for (idx = 0; idx <= xgs; idx++) { swim_put_line(&win1, curx, cury, curx, curym); curx++; } clr = clr + 0x0001; } }
/*********************************************************************** * * Function: ssp_open * * Purpose: Open the SSP * * Processing: * Initializes the SSP clocks and default state. * * Parameters: * ipbase: SSP descriptor device address * arg : Pointer to config structure, or NULL if not used * * Outputs: None * * Returns: The pointer to a SSP config structure or 0 * * Notes: None * **********************************************************************/ INT_32 ssp_open(void *ipbase, INT_32 arg) { SSP_CONFIG_T ssp_cfg, *psspcfg; volatile UNS_32 tmp; SSP_REGS_T *psspregs = (SSP_REGS_T *) ipbase; SSP_DRVDAT_T *psspdrvdat = NULL; INT_32 status = 0; /* Map SSP registers to data index */ if (psspregs == SSP0) { psspdrvdat = (SSP_DRVDAT_T *) & sspdrv [0]; psspdrvdat->thisdev = 0; } else if (psspregs == SSP1) { psspdrvdat = (SSP_DRVDAT_T *) & sspdrv [1]; psspdrvdat->thisdev = 1; } if (psspdrvdat != NULL) { if (psspdrvdat->init == FALSE) { /* Save and return address of peripheral block */ psspdrvdat->regptr = (SSP_REGS_T *) ipbase; /* Enable SSP clock */ clkpwr_clk_en_dis(sspclks[psspdrvdat->thisdev], 1); /* No initial callbacks */ psspdrvdat->cbs.txcb = NULL; psspdrvdat->cbs.rxcb = NULL; /* Initialize device */ if (arg == 0) { /* Create and use defaults */ ssp_cfg.databits = 8; ssp_cfg.mode = SSP_CR0_FRF_SPI; ssp_cfg.highclk_spi_frames = TRUE; ssp_cfg.usesecond_clk_spi = FALSE; ssp_cfg.ssp_clk = 1000000; ssp_cfg.master_mode = TRUE; psspcfg = &ssp_cfg; } else { psspcfg = (SSP_CONFIG_T *) arg; } if (ssp_configure(psspcfg, psspdrvdat) != _ERROR) { /* Device is valid */ psspdrvdat->init = TRUE; status = (INT_32) psspdrvdat; } else { clkpwr_clk_en_dis(sspclks[psspdrvdat->thisdev], 0); } /* Empty FIFO */ while ((psspdrvdat->regptr->sr & SSP_SR_RNE) != 0) { tmp = psspdrvdat->regptr->data; } /* Clear latched interrupts */ psspdrvdat->regptr->icr = (SSP_ICR_RORIC | SSP_ICR_RTIC); /* Enable interrupts */ psspdrvdat->regptr->imsc = (SSP_IMSC_RORIM | SSP_IMSC_RTIM | SSP_IMSC_RXIM); } } return status; }
/*********************************************************************** * * Function: c_entry * * Purpose: Application entry point from the startup code * * Processing: * See function. * * Parameters: None * * Outputs: None * * Returns: Nothing * * Notes: None * **********************************************************************/ void c_entry(void) { static PWM_CHANNEL_SETUP_T pwm_channel_setup[2][7]; static PWM_SYSTEM_SETUP_T pwm_system_setup[2]; static PWM_UPDATE_CONTROL_T pwm_update_control[2]; /* Disable interrupts in ARM core */ disable_irq(); /* Setup miscellaneous board functions */ phy3250_board_init(); /* Set virtual address of MMU table */ cp15_set_vmmu_addr((void *) (IRAM_BASE + (256 * 1024) - (16 * 1024))); /* Initialize interrupt system */ int_initialize(0xFFFFFFFF); /* Install standard IRQ dispatcher at ARM IRQ vector */ int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler); /* Enable IRQ interrupts in the ARM core */ enable_irq(); /* Enable PWM3/4 clocks */ clkpwr_clk_en_dis(CLKPWR_PWM3_CLK, 1); clkpwr_clk_en_dis(CLKPWR_PWM4_CLK, 1); /* Install PWM3 and PWM4 interrupt handlers as a IRQ interrupts */ int_install_ext_irq_handler(IRQ_PWM3, (PFV) pwm3_user_interrupt, ACTIVE_LOW, 1); int_install_ext_irq_handler(IRQ_PWM4, (PFV) pwm4_user_interrupt, ACTIVE_LOW, 1); /* Disable SD/MMC output and select PWM3.x on the SD/MMC pins */ CLKPWR->clkpwr_ms_ctrl = CLKPWR_MSCARD_MSDIO_PIN_DIS; GPIO->p_mux_set = P_MAT21 | P_MAT20 | P_MAT03 | P_MAT02 | P_MAT01 | P_MAT00; /* Select PWM3.x on the LCD pins */ GPIO->p3_mux_set = P3_GPO10_MC2B | P3_GPO12_MC2A | P3_GPO13_MC1B | P3_GPO15_MC1A | P3_GPO16_MC0B | P3_GPO18_MC0A; /* Select PWM4.x on the LCD pins */ GPIO->p3_mux_set = P3_GPO6 | P3_GPO8 | P3_GPO9; /* Loop forever and let the demo syscle thru different steps */ while (1) { /* PWM3/4 clock is the Peripheral clock (13 MHz) */ /* PWM3 and PWM4 are not synchronized */ /* */ /* Seven single edge independently controlled outputs */ /* */ /* PWM3 prescaler: 2, period: 10000 ticks => fout = 650 Hz */ /* channel 1: single edge, duty cycle 14% */ /* channel 2: single edge, duty cycle 28% */ /* channel 3: single edge, duty cycle 42% */ /* channel 4: single edge, duty cycle 56% */ /* channel 5: single edge, duty cycle 70% */ /* channel 6: single edge, duty cycle 84% */ /* */ /* PWM4 prescaler: 2, period: 5000 ticks => fout = 1300 Hz */ /* channel 1: single edge, toggle @ 2000 */ /* channel 2: single edge, toggle @ 3000 */ /* channel 3: single edge, toggle @ 4000 */ /* open PWM3 */ pwmdev1 = pwm_open(PWM3, 0); pwm_ioctl(pwmdev1, PWM_SYSTEM_CONTROL, PWM_TIMER_RESET); pwm_system_setup[0].clock = PWM_CLOCK_PERIPHERAL; pwm_system_setup[0].prescale = 2; pwm_system_setup[0].period = 10000; pwm_system_setup[0].update = PWM_NO_UPDATE; pwm_ioctl(pwmdev1, PWM_SYSTEM_SETUP, (INT_32) &pwm_system_setup[0]); pwm_channel_setup[0][1].channel = 1; pwm_channel_setup[0][1].mode = PWM_SINGLE_EDGE; pwm_channel_setup[0][1].duty_option = PWM_WAV_DUTY_PER; pwm_channel_setup[0][1].duty = 14; pwm_ioctl(pwmdev1, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[0][1]); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_ENABLE, 1); pwm_channel_setup[0][2].channel = 2; pwm_channel_setup[0][2].mode = PWM_SINGLE_EDGE; pwm_channel_setup[0][2].duty_option = PWM_WAV_DUTY_PER; pwm_channel_setup[0][2].duty = 28; pwm_ioctl(pwmdev1, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[0][2]); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_ENABLE, 2); pwm_channel_setup[0][3].channel = 3; pwm_channel_setup[0][3].mode = PWM_SINGLE_EDGE; pwm_channel_setup[0][3].duty_option = PWM_WAV_DUTY_PER; pwm_channel_setup[0][3].duty = 42; pwm_ioctl(pwmdev1, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[0][3]); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_ENABLE, 3); pwm_channel_setup[0][4].channel = 4; pwm_channel_setup[0][4].mode = PWM_SINGLE_EDGE; pwm_channel_setup[0][4].duty_option = PWM_WAV_DUTY_PER; pwm_channel_setup[0][4].duty = 56; pwm_ioctl(pwmdev1, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[0][4]); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_ENABLE, 4); pwm_channel_setup[0][5].channel = 5; pwm_channel_setup[0][5].mode = PWM_SINGLE_EDGE; pwm_channel_setup[0][5].duty_option = PWM_WAV_DUTY_PER; pwm_channel_setup[0][5].duty = 70; pwm_ioctl(pwmdev1, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[0][5]); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_ENABLE, 5); pwm_channel_setup[0][6].channel = 6; pwm_channel_setup[0][6].mode = PWM_SINGLE_EDGE; pwm_channel_setup[0][6].duty_option = PWM_WAV_DUTY_PER; pwm_channel_setup[0][6].duty = 84; pwm_ioctl(pwmdev1, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[0][6]); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_ENABLE, 6); pwm_update_control[0].update = PWM_UPDATE; pwm_update_control[0].channels = 0x7E; pwm_ioctl(pwmdev1, PWM_UPDATE_CONTROL, (INT_32) &pwm_update_control[0]); pwm_ioctl(pwmdev1, PWM_SYSTEM_CONTROL, PWM_TIMER_RESTART); /* open PWM4 */ pwmdev2 = pwm_open(PWM4, 0); pwm_system_setup[1].clock = PWM_CLOCK_PERIPHERAL; pwm_system_setup[1].prescale = 2; pwm_system_setup[1].period = 5000; pwm_system_setup[1].update = PWM_NO_UPDATE; pwm_ioctl(pwmdev2, PWM_SYSTEM_SETUP, (INT_32) &pwm_system_setup[1]); pwm_channel_setup[1][1].channel = 1; pwm_channel_setup[1][1].mode = PWM_SINGLE_EDGE; pwm_channel_setup[1][1].duty_option = PWM_WAV_DUTY_ABS; pwm_channel_setup[1][1].duty = 2000; pwm_ioctl(pwmdev2, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[1][1]); pwm_ioctl(pwmdev2, PWM_CHANNEL_OUT_ENABLE, 1); pwm_channel_setup[1][2].channel = 2; pwm_channel_setup[1][2].mode = PWM_SINGLE_EDGE; pwm_channel_setup[1][2].duty_option = PWM_WAV_DUTY_ABS; pwm_channel_setup[1][2].duty = 3000; pwm_ioctl(pwmdev2, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[1][2]); pwm_ioctl(pwmdev2, PWM_CHANNEL_OUT_ENABLE, 2); pwm_channel_setup[1][3].channel = 3; pwm_channel_setup[1][3].mode = PWM_SINGLE_EDGE; pwm_channel_setup[1][3].duty_option = PWM_WAV_DUTY_ABS; pwm_channel_setup[1][3].duty = 4000; pwm_ioctl(pwmdev2, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[1][3]); pwm_ioctl(pwmdev2, PWM_CHANNEL_OUT_ENABLE, 3); pwm_update_control[1].update = PWM_UPDATE; pwm_update_control[1].channels = 0x0E; pwm_ioctl(pwmdev2, PWM_UPDATE_CONTROL, (INT_32) &pwm_update_control[1]); pwm_ioctl(pwmdev2, PWM_SYSTEM_CONTROL, PWM_TIMER_RESTART); delay(2500000); /* close PWM3 & PWM4 */ pwm_close(pwmdev1); pwm_close(pwmdev2); delay(2500000); /* PWM3/4 clock is the Peripheral clock (13 MHz) */ /* PWM3 and PWM4 are synchronized */ /* */ /* Four dual edge controlled outputs PWM3.2/4/6 and PWM4.2 */ /* (as in a stepper motor control application) and a single */ /* edge independently controlled output PWM4.3 */ /* PWM3.1/3/5 are disabled */ /* */ /* PWM3 prescaler: 5, period: 10000 ticks => fout = 260 Hz */ /* channel 1: disabled */ /* channel 2: dual edge, duty cycle 80%, offset 5% */ /* channel 3: disabled */ /* channel 4: dual edge, duty cycle 80% offset 30% */ /* channel 5: disabled */ /* channel 6: dual edge, duty cycle 80% offset 55% */ /* */ /* PWM4 prescaler: 5, period: 10000 ticks => fout = 260 Hz */ /* channel 1: disabled */ /* channel 2: dual edge, duty cycle 80% offset 80% */ /* channel 3: single edge, toggle @ 500 */ /* open PWM3 */ pwmdev1 = pwm_open(PWM3, 0); pwm_ioctl(pwmdev1, PWM_SYSTEM_CONTROL, PWM_TIMER_RESET); pwm_system_setup[0].clock = PWM_CLOCK_PERIPHERAL; pwm_system_setup[0].prescale = 5; pwm_system_setup[0].period = 10000; pwm_system_setup[0].update = PWM_NO_UPDATE; pwm_ioctl(pwmdev1, PWM_SYSTEM_SETUP, (INT_32) &pwm_system_setup[0]); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_DISABLE, 1); pwm_channel_setup[0][2].channel = 2; pwm_channel_setup[0][2].mode = PWM_DUAL_EDGE; pwm_channel_setup[0][2].duty_option = PWM_WAV_DUTY_PER; pwm_channel_setup[0][2].duty = 80; pwm_channel_setup[0][2].offset_option = PWM_WAV_OFFSET_PER; pwm_channel_setup[0][2].offset = 5; pwm_channel_setup[0][2].ini_state = 1; pwm_ioctl(pwmdev1, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[0][2]); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_ENABLE, 2); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_DISABLE, 3); pwm_channel_setup[0][4].channel = 4; pwm_channel_setup[0][4].mode = PWM_DUAL_EDGE; pwm_channel_setup[0][4].duty_option = PWM_WAV_DUTY_PER; pwm_channel_setup[0][4].duty = 80; pwm_channel_setup[0][4].offset_option = PWM_WAV_OFFSET_PER; pwm_channel_setup[0][4].offset = 30; pwm_channel_setup[0][4].ini_state = 1; pwm_ioctl(pwmdev1, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[0][4]); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_ENABLE, 4); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_DISABLE, 5); pwm_channel_setup[0][6].channel = 6; pwm_channel_setup[0][6].mode = PWM_DUAL_EDGE; pwm_channel_setup[0][6].duty_option = PWM_WAV_DUTY_PER; pwm_channel_setup[0][6].duty = 80; pwm_channel_setup[0][6].offset_option = PWM_WAV_OFFSET_PER; pwm_channel_setup[0][6].offset = 55; pwm_channel_setup[0][6].ini_state = 1; pwm_ioctl(pwmdev1, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[0][6]); pwm_ioctl(pwmdev1, PWM_CHANNEL_OUT_ENABLE, 6); pwm_update_control[0].update = PWM_UPDATE; pwm_update_control[0].channels = 0x7E; pwm_ioctl(pwmdev1, PWM_UPDATE_CONTROL, (INT_32) &pwm_update_control[0]); /* open PWM4 */ pwmdev2 = pwm_open(PWM4, 0); pwm_system_setup[1].clock = PWM_CLOCK_PERIPHERAL; pwm_system_setup[1].prescale = 5; pwm_system_setup[1].period = 10000; pwm_system_setup[1].update = PWM_NO_UPDATE; pwm_ioctl(pwmdev2, PWM_SYSTEM_SETUP, (INT_32) &pwm_system_setup[1]); pwm_channel_setup[1][2].channel = 2; pwm_channel_setup[1][2].mode = PWM_DUAL_EDGE; pwm_channel_setup[1][2].duty_option = PWM_WAV_DUTY_PER; pwm_channel_setup[1][2].duty = 80; pwm_channel_setup[1][2].offset_option = PWM_WAV_OFFSET_PER; pwm_channel_setup[1][2].offset = 80; pwm_channel_setup[1][2].ini_state = 1; pwm_ioctl(pwmdev2, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[1][2]); pwm_ioctl(pwmdev2, PWM_CHANNEL_OUT_ENABLE, 2); pwm_channel_setup[1][3].channel = 3; pwm_channel_setup[1][3].mode = PWM_SINGLE_EDGE; pwm_channel_setup[1][3].duty_option = PWM_WAV_DUTY_ABS; pwm_channel_setup[1][3].duty = 500; pwm_ioctl(pwmdev2, PWM_CHANNEL_SETUP, (INT_32) &pwm_channel_setup[1][3]); pwm_ioctl(pwmdev2, PWM_CHANNEL_OUT_ENABLE, 3); pwm_update_control[1].update = PWM_UPDATE; pwm_update_control[1].channels = 0x0E; pwm_ioctl(pwmdev2, PWM_UPDATE_CONTROL, (INT_32) &pwm_update_control[1]); pwm_ioctl(pwmdev1, PWM_SYSTEM_CONTROL, PWM_TIMER_SYNC); pwm_ioctl(pwmdev2, PWM_SYSTEM_CONTROL, PWM_TIMER_RESTART); pwm_ioctl(pwmdev1, PWM_SYSTEM_CONTROL, PWM_TIMER_GO); delay(2500000); /* close PWM3 & PWM4 */ pwm_close(pwmdev1); pwm_close(pwmdev2); delay(2500000); } }
/*********************************************************************** * * Function: c_entry * * Purpose: Application entry point from the startup code * * Processing: * See function. * * Parameters: None * * Outputs: None * * Returns: Always returns 1, or <0 on an error * * Notes: None * **********************************************************************/ int c_entry(void) { SWIM_WINDOW_T win1; COLOR_T *fblog; INT_32 lcddev; /* Disable interrupts in ARM core */ disable_irq_fiq(); /* Setup miscellaneous board functions */ phy3250_board_init(); /* Set virtual address of MMU table */ cp15_set_vmmu_addr((void *) (IRAM_BASE + (256 * 1024) - (16 * 1024))); /* Initialize interrupt system */ int_initialize(0xFFFFFFFF); /* Install standard IRQ dispatcher at ARM IRQ vector */ int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler); /* Install RTC interrupt handler as a IRQ interrupts */ int_install_irq_handler(IRQ_RTC, (PFV) rtc_user_interrupt); /* Open RTC */ rtcdev = rtc_open(RTC, 0); if (rtcdev == 0) { /* Error */ return -1; } /* Set a 1s match rate */ secs = lsecs = 0; mstp.match_num = 0; mstp.use_match_int = TRUE; mstp.enable_onsw = FALSE; mstp.match_tick_val = secs + 1; rtc_ioctl(rtcdev, RTC_ENABLE, 0); rtc_ioctl(rtcdev, RTC_SET_COUNT, 0); rtc_ioctl(rtcdev, RTC_CLEAR_INTS, RTC_MATCH0_INT_STS); rtc_ioctl(rtcdev, RTC_SETUP_MATCH, (INT_32) &mstp); /* Setup LCD muxing for STN Color 16BPP */ clkpwr_setup_lcd(CLKPWR_LCDMUX_TFT16, 1); /* Enable clock to LCD block (HCLK_EN)*/ clkpwr_clk_en_dis(CLKPWR_LCD_CLK, 1); /* Setup LCD paramaters in the LCD controller */ lcddev = lcd_open(CLCDC, (INT_32) & LCD_DISPLAY); /* Upper Panel Frame Base Address register */ lcd_ioctl(lcddev, LCD_SET_UP_FB, PHY_LCD_FRAME_BUF); /* Enable LCD controller and power signals */ lcd_ioctl(lcddev, LCD_PWENABLE, 1); /* Enable LCD backlight */ phy3250_lcd_backlight_enable(TRUE); /* Enable LCD power */ phy3250_lcd_power_enable(TRUE); /* Set frame buffer address */ fblog = (COLOR_T *) cp15_map_physical_to_virtual(PHY_LCD_FRAME_BUF); /* Create a SWIM window */ swim_window_open(&win1, LCD_DISPLAY.pixels_per_line, LCD_DISPLAY.lines_per_panel, fblog, 0, 0, (LCD_DISPLAY.pixels_per_line - 1), (LCD_DISPLAY.lines_per_panel - 1), 1, WHITE, BLACK, BLACK); swim_put_ltext(&win1, "RTC example: This example will print the message " "TICK whenever an RTC interrupt occurs (1 second intervals). It will " "quit after 10 seconds\n"); /* Enable RTC (starts counting) */ rtc_ioctl(rtcdev, RTC_ENABLE, 1); /* Enable RTC interrupt in the interrupt controller */ int_enable(IRQ_RTC); /* Enable IRQ interrupts in the ARM core */ enable_irq(); /* Loop for 10 seconds and let interrupts toggle the LEDs */ while (secs < 10) { if (lsecs < secs) { swim_put_ltext(&win1, "TICK\n"); lsecs = secs; } } /* Disable RTC interrupt in the interrupt controller */ int_disable(IRQ_RTC); /* Disable interrupts in ARM core */ disable_irq_fiq(); /* Prior to closing the RTC, the ONSW key value is set. This will allow the RTC to keep it's value across resets as long as RTC power is maintained */ rtc_ioctl(rtcdev, RTC_SETCLR_KEY, 1); /* Close RTC and LCD */ rtc_close(rtcdev); lcd_close(lcddev); return 1; }
/*********************************************************************** * * Function: c_entry * * Purpose: Application entry point from the startup code * * Processing: * See function. * * Parameters: None * * Outputs: None * * Returns: Always returns 1, or <0 on an error * * Notes: None * **********************************************************************/ int c_entry(void) { /* Disable interrupts in ARM core */ disable_irq_fiq(); /* Setup miscellaneous board functions */ phy3250_board_init(); /* Set virtual address of MMU table */ cp15_set_vmmu_addr((void *) (IRAM_BASE + (256 * 1024) - (16 * 1024))); /* Initialize interrupt system */ int_initialize(0xFFFFFFFF); /* Install standard IRQ dispatcher at ARM IRQ vector */ int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler); /* Enable simple WDT clock */ clkpwr_clk_en_dis(CLKPWR_WDOG_CLK, 1); /* Install WDT interrupt handler as an IRQ interrupt */ int_install_ext_irq_handler(IRQ_WATCH, (PFV) wdt_user_interrupt, ACTIVE_HIGH, 1); /* Open WDT */ wdtdev = wdt_open(WDT, 0); if (wdtdev == 0) { /* Error */ return -1; } /* Enable IRQ interrupts in the ARM core */ enable_irq(); /* Drive RESETOUT high/low/high using RESFRC1 */ wdtsetup.initial_setup = TRUE; wdtsetup.pause = 1; wdtsetup.resfrc2 = 0; wdtsetup.resfrc1 = 0; wdtsetup.m_res2 = 0; wdtsetup.m_res1 = 0; wdtsetup.ext_match_setup = WDT_EXT_MATCH_IDLE; wdtsetup.match_setup = WDT_MATCH_IDLE; wdtsetup.match0_update = FALSE; wdtsetup.counter_update = FALSE; wdtsetup.pulse_update = FALSE; wdt_ioctl(wdtdev, WDT_SETUP, (UNS_32) &wdtsetup); delay(10000); wdtsetup.resfrc1 = 1; wdt_ioctl(wdtdev, WDT_SETUP, (UNS_32) &wdtsetup); delay(10000); wdtsetup.resfrc1 = 0; wdt_ioctl(wdtdev, WDT_SETUP, (UNS_32) &wdtsetup); delay(10000); #ifdef RESET_CHIP_example /* generate a 10 ms delay followed by a 3 ms */ /* RESETOUT pulse using M_RES2 = 1 */ wdt_ioctl(wdtdev, WDT_TIMER_STOP, 0); wdt_ioctl(wdtdev, WDT_INT_DISABLE, 0); wdt_ioctl(wdtdev, WDT_INT_CLEAR, 0); wdtsetup.initial_setup = TRUE; wdtsetup.pause = 1; wdtsetup.resfrc2 = 0; wdtsetup.resfrc1 = 0; wdtsetup.m_res2 = 1; wdtsetup.m_res1 = 0; wdtsetup.ext_match_setup = WDT_EXT_MATCH_HIGH; wdtsetup.match_setup = WDT_MATCH_EN_INT_RESET; wdtsetup.match0 = 10 * 13000; wdtsetup.match0_update = TRUE; wdtsetup.counter_update = FALSE; wdtsetup.pulse = 3 * 13000 - 5; wdtsetup.pulse_update = TRUE; wdt_ioctl(wdtdev, WDT_SETUP, (UNS_32) &wdtsetup); wdt_ioctl(wdtdev, WDT_INT_CLEAR, 0); wdt_ioctl(wdtdev, WDT_INT_ENABLE, 0); int_enable(IRQ_WATCH); while (1); #endif /* Close WDT */ wdt_close(wdtdev); return 1; }
/********************************************************************** * * Function: c_entry * * Purpose: Application entry point from the startup code * * Processing: * See function. * * Parameters: None * * Outputs: None * * Returns: Nothing * * Notes: None * *********************************************************************/ void c_entry(void) { SWIM_WINDOW_T win1; COLOR_T clr, *fblog; int idx; UNS_16 xgs, ygs, curx, cury, curym, xidx; /* Disable interrupts in ARM core */ disable_irq_fiq(); /* Set virtual address of MMU table */ cp15_set_vmmu_addr((void *) (IRAM_BASE + (256 * 1024) - (16 * 1024))); /* Initialize interrupt system */ int_initialize(0xFFFFFFFF); /* Install standard IRQ dispatcher at ARM IRQ vector */ int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler); /* Setup miscellaneous board functions */ phy3250_board_init(); /* enable clock to ADC block - 32KHz clock */ clkpwr_clk_en_dis(CLKPWR_ADC_CLK,1); /* TSC IRQ goes active when the FIFO reaches the Interrupt level */ int_install_irq_handler(IRQ_TS_IRQ, (PFV) tsc_user_interrupt); /* Enable interrupt */ int_enable(IRQ_TS_IRQ); /* Open TSC, sets default timing values, fifo = 16, resolution = 10bits */ tscdev = tsc_open(TSC, 0); /* TSC Auto mode enable, this also sets AUTO bit */ tsc_ioctl(tscdev,TSC_AUTO_EN, 1); /* Setup LCD muxing for STN Color 16BPP */ clkpwr_setup_lcd(CLKPWR_LCDMUX_TFT16, 1); /* Enable clock to LCD block (HCLK_EN)*/ clkpwr_clk_en_dis(CLKPWR_LCD_CLK, 1); /* Setup LCD paramaters in the LCD controller */ lcddev = lcd_open(CLCDC, (INT_32) &LCD_DISPLAY); /* Upper Panel Frame Base Address register */ lcd_ioctl(lcddev, LCD_SET_UP_FB, PHY_LCD_FRAME_BUF); /* Enable LCD controller and power signals */ lcd_ioctl(lcddev, LCD_PWENABLE, 1); /* Enable LCD backlight */ phy3250_lcd_backlight_enable(TRUE); /* Enable LCD power */ phy3250_lcd_power_enable(TRUE); /* write cursor image array data to cursor image RAM */ lcd_ioctl(lcddev, LCD_CRSR_INIT_IMG, (INT_32) &cursorimage[0]); /* enable the default cursor 0 */ lcd_ioctl(lcddev,LCD_CRSR_EN,1); /* set the cursor X/Y position */ lcd_ioctl(lcddev, LCD_CRSR_XY, 0x0); /* set the cursor pallette BGR value, col0*/ lcd_ioctl(lcddev, LCD_CRSR_PAL0, 0x00ff0000); /* set the cursor pallette BGR value, col1 */ lcd_ioctl(lcddev, LCD_CRSR_PAL1, 0x000000ff); /* Enable IRQ interrupts in the ARM core */ enable_irq(); /* Set frame buffer address */ fblog = (COLOR_T *)cp15_map_physical_to_virtual(PHY_LCD_FRAME_BUF); /* Create a SWIM window */ swim_window_open(&win1, LCD_DISPLAY.pixels_per_line, LCD_DISPLAY.lines_per_panel, fblog, 0, 0, (LCD_DISPLAY.pixels_per_line - 1), (LCD_DISPLAY.lines_per_panel - 1), 1, WHITE, BLACK, BLACK); /* Compute vertical size for bars */ ygs = LCD_DISPLAY.lines_per_panel / 3; /* Draw Red bars */ cury = 0; curx = 0; curym = ygs - 1; xgs = LCD_DISPLAY.pixels_per_line / RED_COLORS; clr = BLACK; for (xidx = 0; xidx < RED_COLORS; xidx++) { swim_set_pen_color(&win1, clr); for (idx = 0; idx <= xgs; idx++) { swim_put_line(&win1, curx, cury, curx, curym); curx++; } clr = clr + 0x0800; } /* Draw green bars */ cury = cury + ygs; curx = 0; curym = cury + (ygs - 1); xgs = LCD_DISPLAY.pixels_per_line / GREEN_COLORS; clr = BLACK; for (xidx = 0; xidx < GREEN_COLORS; xidx++) { swim_set_pen_color(&win1, clr); for (idx = 0; idx <= xgs; idx++) { swim_put_line(&win1, curx, cury, curx, curym); curx++; } clr = clr + 0x0020; } /* Draw blue bars */ cury = cury + ygs; curx = 0; curym = cury + (ygs - 1); xgs = LCD_DISPLAY.pixels_per_line / BLUE_COLORS; clr = BLACK; for (xidx = 0; xidx < BLUE_COLORS; xidx++) { swim_set_pen_color(&win1, clr); for (idx = 0; idx <= xgs; idx++) { swim_put_line(&win1, curx, cury, curx, curym); curx++; } clr = clr + 0x0001; } /* lets stay here forever */ while(1); }
/********************************************** ИНИЦИАЛИЗАЦИЯ СИСТЕМЫ ПРЕРЫВАНИЙ **********************************************/ void InitializeInterruptSystem() { /* Initialize interrupt system */ int_initialize(0xFFFFFFFF); /* Install standard IRQ dispatcher at ARM IRQ vector */ int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler); /* Install standard FIQ dispatcher at ARM IRQ vector */ int_install_arm_vec_handler(FIQ_VEC, (PFV) lpc32xx_fiq_handler); //---------------------HSTIMER------------------------------------ /* Install HSTIMER interrupt handler as a IRQ interrupts */ int_install_irq_handler(IRQ_HSTIMER, (PFV) hstimer_user_interrupt); // Save address of register block hst_regptr = HSTIMER; gpio_regptr = GPIO; // LEDs off //gpio_regptr->p3_outp_clr = LED1 | LED2; //gpio_regptr->p1_dir_set = LED3; // Enable timer system clock clkpwr_clk_en_dis(CLKPWR_HSTIMER_CLK, 1); // Disable high speed timer and match timers hst_regptr->hstim_ctrl = HSTIM_CTRL_RESET_COUNT; hst_regptr->hstim_mctrl = 0; hst_regptr->hstim_ctrl = 0; // Clear pending interrupts hst_regptr->hstim_int = (HSTIM_MATCH0_INT | HSTIM_MATCH1_INT | HSTIM_MATCH2_INT | HSTIM_GPI_06_INT | HSTIM_RTC_TICK_INT); hst_regptr->hstim_mctrl = HSTIM_CNTR_MCR_MTCH(0) | HSTIM_CNTR_MCR_RESET(0); hst_regptr->hstim_pmatch = 13-1; hst_regptr->hstim_match[0] = 1000;//1ms 000; hst_regptr->hstim_ctrl = HSTIM_CTRL_COUNT_ENAB;//start hstimer // Enable interrupt in the interrupt controller int_enable(IRQ_HSTIMER); //---------------------SSP1------------------------------------ ssp1_regptr = SSP1; // Pointer to SSP1 registers // Enable ssp1 system clock clkpwr_clk_en_dis(CLKPWR_SSP1_CLK, 1); //конфигурация IO gpio_regptr->p2_mux_clr = P2_GPIO04_SSEL1; gpio_regptr->p2_dir_set = P2_DIR_GPIO(4); gpio_regptr->p3_outp_set = P3_STATE_GPIO(4); /* The MISO, MOSI, and SCK signals are controlled by the SSP1 */ gpio_regptr->p_mux_set = (P_SPI2DATAIO_MOSI1 | P_SPI2DATAIN_MISO1 | P_SPI2CLK_SCK1); ssp1_regptr->cpsr = SSP_CPSR_CPDVSR(16);//8);//4);//4);//prescale //ssp_clk / ((cr0_div + 1) * prescale); //prescale = 16; SCR = 4 - 1.25MGz ssp1_regptr->cr0 = SSP_CR0_DSS(8) |//data size 8 bit SSP_CR0_FRF_SPI |//Motorola SPI mode SSP_CR0_SCR(4);//serial clock rate // Default Master mode // Disable SSP1 ssp1_regptr->cr1 &= ~SSP_CR1_SSP_ENABLE; // interr handler SSP1 IRQ //int_install_irq_handler(IRQ_SSP1, (PFV) ssp1_user_interrupt); // Enable interrupt in the interrupt controller //int_enable(IRQ_SSP1); // Clear interrupt in the interrupt controller //int_clear(IRQ_SSP1); // Enable SSP1 ssp1_regptr->cr1 |= SSP_CR1_SSP_ENABLE; }//InitializeInterruptSystem()
void c_entry(void) { static I2C_SETUP_T i2c_setup[2]; static volatile I2C_MTX_SETUP_T i2c_mtx_setup; static I2C_MTXRX_SETUP_T i2c_mtxrx_setup; static I2C_MRX_SETUP_T i2c_mrx_setup; UNS_8 rx_data[16], tx_data[16]; /* Disable interrupts in ARM core */ disable_irq(); /* Setup miscellaneous board functions */ ea3250_board_init(); /* Set virtual address of MMU table */ cp15_set_vmmu_addr((void *) (IRAM_BASE + (256 * 1024) - (16 * 1024))); /* Initialize interrupt system */ int_initialize(0xFFFFFFFF); /* Install standard IRQ dispatcher at ARM IRQ vector */ int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler); /* Enable I2C1/2 clock */ clkpwr_clk_en_dis(CLKPWR_I2C1_CLK,1); clkpwr_clk_en_dis(CLKPWR_I2C2_CLK,1); /* install default I2C1 & I2C2 interrupt handlers */ int_install_ext_irq_handler(IRQ_I2C_1, (PFV) i2c1_user_interrupt, ACTIVE_LOW, 1); int_install_ext_irq_handler(IRQ_I2C_2, (PFV) i2c2_user_interrupt, ACTIVE_LOW, 1); /* Enable IRQ interrupts in the ARM core */ enable_irq(); /* open I2C1 */ i2cdev1 = i2c_open(I2C1, 0); /* formally assign a 7-bit slave address 0x50 to I2C1 */ /* I2C1 clock is 100 kHz, 50% duty cycle, high pin drive */ i2c_setup[0].addr_mode = ADDR7BIT; // i2c_setup[0].sl_addr = 0x60; i2c_setup[0].rate_option= I2C_RATE_RELATIVE; i2c_setup[0].rate = 100000; i2c_setup[0].low_phase = 50; i2c_setup[0].high_phase = 50; i2c_setup[0].pins_drive = I2C_PINS_HIGH_DRIVE; i2c_ioctl((UNS_32) i2cdev1, I2C_SETUP, (UNS_32) &i2c_setup[0]); /* Write 9 bytes to PCA9532 and init registers, starting with reg 0x02 + auto increment = 0x10 */ tx_data[0] = 0x12; tx_data[1] = 151; /*PSC0 = blink 1s*/ tx_data[2] = 256/3; /*PWM0 1/3 duty cycle*/ tx_data[3] = 0; /*PSC1 = blink 1/152s*/ tx_data[4] = 256/32;/*PWM1 = 1/32 duty cycle*/ tx_data[5] = 0x00; /*LS0 outputs 0 - 3 High impedance*/ tx_data[6] = 0x00; /*LS1 outputs 4 - 7 High impedance*/ tx_data[7] = 0xE4; /*LS2 output 8 High impedance (LED1 OFF) output 9 LOW (LED2 ON) output 10 blinks at PWM0 rate output 11 blinks at PWM1 rate*/ tx_data[8] = 0xE4; /*LS2 output 12 High impedance (LED1 OFF) output 13 LOW (LED2 ON) output 14 blinks at PWM0 rate output 15 blinks at PWM1 rate*/ i2c_mtx_setup.addr_mode = ADDR7BIT; i2c_mtx_setup.sl_addr = 0x60; i2c_mtx_setup.tx_data = &tx_data[0]; i2c_mtx_setup.tx_length = 9; i2c_mtx_setup.retransmissions_max = 10; i2c_ioctl(i2cdev1, I2C_MASTER_TX, (INT_32)&i2c_mtx_setup); while (( i2c_mtx_setup.status & I2C_SETUP_STATUS_DONE) == 0 /*&& mtx_irq < 100000*/); i2c_close(i2cdev1); }
/*********************************************************************** * * Function: c_entry * * Purpose: Application entry point from the startup code * * Processing: * See function. * * Parameters: None * * Outputs: None * * Returns: Nothing * * Notes: None * **********************************************************************/ void c_entry(void) { SPWM_SETUP_T spwmsetup[2]; /* Disable interrupts in ARM core */ disable_irq(); /* Setup miscellaneous board functions */ phy3250_board_init(); /* Set virtual address of MMU table */ cp15_set_vmmu_addr((void *) (IRAM_BASE + (256 * 1024) - (16 * 1024))); /* Initialize interrupt system */ int_initialize(0xFFFFFFFF); /* Install standard IRQ dispatcher at ARM IRQ vector */ int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler); /* Enable IRQ interrupts in the ARM core */ enable_irq(); /* Enable simple PWM1/2 clocks*/ clkpwr_clk_en_dis(CLKPWR_PWM1_CLK, 1); clkpwr_clk_en_dis(CLKPWR_PWM2_CLK, 1); /* Loop forever and let the demo syscle thru different steps */ while (1) { /* open PWM1 */ spwmdev1 = spwm_open(PWM1, 0); /* Select PERIPH_CLK for PWM1 and set divider to 4 */ clkpwr_setup_pwm(1, 1, 4); /* open PWM2 */ spwmdev2 = spwm_open(PWM2, 0); /* Select 32768 Hz for PWM2 and set divider to 1 */ clkpwr_setup_pwm(2, 0, 1); /* PWM1 duty cycle = 30%, reload = 8 */ /* fout1 = 13 MHz / (4*8*256) = 1.587 kHz */ spwmsetup[0].reload = 8; spwmsetup[0].duty_per = 30; spwm_ioctl(spwmdev1, SPWM_SETUP, (INT_32) &spwmsetup[0]); /* PWM2 duty cycle = 85%, reload = 2 */ /* fout2 = 32768 Hz / (1*2*256) = 64 Hz */ spwmsetup[1].reload = 2; spwmsetup[1].duty_per = 85; spwm_ioctl(spwmdev2, SPWM_SETUP, (INT_32) &spwmsetup[1]); delay(2500000); /* Drive PWM1 low <=> 0% duty cycle */ spwm_ioctl(spwmdev1, SPWM_DUTY_PER, 0); /* Drive PWM2 low <=> 0% duty cycle */ spwm_ioctl(spwmdev2, SPWM_DUTY_PER, 0); delay(2500000); /* PWM1 duty cycle 10% */ spwm_ioctl(spwmdev1, SPWM_DUTY_PER, 10); /* Drive PWM2 high <=> 100% duty cycle */ spwm_ioctl(spwmdev2, SPWM_DUTY_PER, 100); delay(1000000); /* PWM1 duty cycle 50% */ spwm_ioctl(spwmdev1, SPWM_DUTY_PER, 50); /* Drive PWM2 low <=> 0% duty cycle */ spwm_ioctl(spwmdev2, SPWM_DUTY_PER, 0); delay(1000000); /* PWM1 duty cycle 75% */ spwm_ioctl(spwmdev1, SPWM_DUTY_PER, 75); /* Drive PWM2 high <=> 100% duty cycle */ spwm_ioctl(spwmdev2, SPWM_DUTY_PER, 100); delay(1000000); /* Drive PWM1 low <=> 0% duty cycle */ spwm_ioctl(spwmdev1, SPWM_DUTY_PER, 0); /* Drive PWM2 low <=> 0% duty cycle */ spwm_ioctl(spwmdev2, SPWM_DUTY_PER, 0); /* close both simple PWMs: PWM1 & PWM2 */ spwm_close(spwmdev1); spwm_close(spwmdev2); delay(2500000); } }