static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
write32(&clk_rst->clk_src_uarta, PLLP << CLK_SOURCE_SHIFT);
clock_configure_source(mselect, PLLP, 102000);
/* The PMIC is on I2C5 and can run at 400 KHz. */
clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
/* TODO: We should be able to set this to 50MHz, but that did not seem
* reliable. */
clock_configure_source(sbc4, PLLP, 33333);
}
static void set_clock_sources(void)
{
/*
* The max98090 codec and the temperature sensor are on I2C1. These
* can both run at 400 KHz, but the kernel sets the bus to 100 KHz.
*/
clock_configure_i2c_scl_freq(i2c1, PLLP, 100);
/*
* MMC3 and MMC4: Set base clock frequency for SD Clock to Tegra MMC's
* maximum speed (48MHz) so we can change SDCLK by second stage divisor
* in payloads, without touching base clock.
*/
clock_configure_source(sdmmc3, PLLP, 48000);
clock_configure_source(sdmmc4, PLLP, 48000);
/* External peripheral 1: audio codec (max98090) using 12MHz CLK1.
* Note the source id of CLK_M for EXTPERIPH1 is 3. */
clock_configure_irregular_source(extperiph1, CLK_M, 12000, 3);
/*
* We need 1.5MHz. So, we use CLK_M. CLK_DIVIDER macro returns a divisor
* (0xe) a little bit off from the ideal value (0xd) but it's good
* enough for beeps. The source id of CLK_M for I2S is 6.
*/
clock_configure_irregular_source(i2s1, CLK_M, 1500, 6);
/* Note source id of PLLP for HOST1x is 4. */
clock_configure_irregular_source(host1x, PLLP, 408000, 4);
/* Use PLLD_OUT0 as clock source for disp1 */
clrsetbits_le32(&clk_rst->clk_src_disp1,
CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
}
static void configure_tpm_i2c_bus(void)
{
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}
