int main(int argc, char *argv[]) { unsigned val; nf2.device_name = DEFAULT_IFACE; processArgs(argc, argv); // Open the interface if possible if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } // Increment the argument pointer argc -= optind; argv += optind; // Read the registers readRegisters(argc, argv); closeDescriptor(&nf2); return 0; }
/* Function declarations */ int main(int argc, char *argv[]) { unsigned value; nf2.device_name = DEFAULT_IFACE; // Open the interface if possible if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } // FIXME: Perform the actual register read and print the value readReg(&nf2, CRYPTO_KEY_REG, &value); printf("Register Key is %x", value); closeDescriptor(&nf2); return 0; }
/* Function declarations */ int main(int argc, char *argv[]) { unsigned value; nf2.device_name = DEFAULT_IFACE; // Open the interface if possible if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } // FIXME: Perform the actual register read and print the value //readReg(&nf2, addr, &value); //printf(...) closeDescriptor(&nf2); return 0; }
int main(int argc, char *argv[]) { unsigned val; for (val=0;val<8;val++) { lost[val] = 0; stored[val]=0; removed[val]=0; } nf2.device_name = DEFAULT_IFACE; if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } w = initscr(); cbreak(); noecho(); show_stats(); closeDescriptor(&nf2); endwin(); return 0; }
int main(int argc, char *argv[]) { nf2.device_name = DEFAULT_IFACE; processArgs(argc, argv); // Open the interface if possible if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } if(argc > 5){ printf("Numero de argumentos deve ser < 4\n"); argc=5; } for(int i=0; i< argc-1; i++){ pdrop[i] = atoi(argv[i+1]); } dumpCounts(); closeDescriptor(&nf2); return 0; }
/* Checks for commandline args, intializes globals, then begins code download. */ int main(int argc, char **argv) { nf2.device_name = DEFAULT_IFACE; processArgs(argc, argv); if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } if (strncmp(log_file_name, "stdout",6)) { if ((log_file = fopen(log_file_name, "w")) == NULL) { printf("Error: unable to open logfile %s for writing.\n", log_file_name); exit(1); } } else log_file = stdout; InitGlobals(); BeginCodeDownload(bin_file_name); if (!cpci_reprog) ResetDevice(); /* reset the PHYs */ NF2_WR32(MDIO_0_CONTROL_REG, 0x8000); NF2_WR32(MDIO_1_CONTROL_REG, 0x8000); NF2_WR32(MDIO_2_CONTROL_REG, 0x8000); NF2_WR32(MDIO_3_CONTROL_REG, 0x8000); /* wait until the resets have been completed */ usleep(100); if (intr_enable) { /* PHY interrupt mask off for link status change */ NF2_WR32(MDIO_0_INTERRUPT_MASK_REG, 0xfffd); NF2_WR32(MDIO_1_INTERRUPT_MASK_REG, 0xfffd); NF2_WR32(MDIO_2_INTERRUPT_MASK_REG, 0xfffd); NF2_WR32(MDIO_3_INTERRUPT_MASK_REG, 0xfffd); } VerifyDevInfo(); fclose(log_file); closeDescriptor(&nf2); return SUCCESS; }
/* closes all open interfaces */ void close_interfaces(struct nf2device **nf2devices, int num_netfpgas) { int i; for (i=0; i<num_netfpgas; i++) { closeDescriptor(nf2devices[i]); free(nf2devices[i]->device_name); free(nf2devices[i]); } }
void router_destroy( router_t* router ) { pthread_mutex_destroy( &router->intf_lock ); #ifdef _CPUMODE_ closeDescriptor( &router->nf ); #endif #ifndef _THREAD_PER_PACKET_ wq_destroy( &router->work_queue ); #endif }
void set_register(unsigned reg, unsigned val) { struct nf2device nf2; nf2.device_name = "nf2c0"; check_iface(&nf2); openDescriptor(&nf2); writeReg(&nf2, reg, val); closeDescriptor(&nf2); }
unsigned get_register(unsigned reg) { struct nf2device nf2; unsigned val; nf2.device_name = "nf2c0"; check_iface(&nf2); openDescriptor(&nf2); readReg(&nf2, reg, &val); closeDescriptor(&nf2); return val; }
int main (int argc,char *argv[]) { unsigned long q0_val, q1_val, q2_val, q3_val, ewma_val; unsigned long q0_val_old, q1_val_old, q2_val_old, q3_val_old; unsigned long b0, b1, b2, b3; unsigned long overall; pthread_t governor_thread; struct struct_thread *param_thread = NULL; /********* NF2 INITIALIZATION **********************/ nf2.device_name = DEFAULT_IFACE; if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } /********* END NF2 INITIALIZATION ******************/ param_thread = (struct struct_thread *)malloc(sizeof(struct struct_thread)); param_thread->nf2 = nf2; param_thread->microseconds_to_sleep = MICROSECONDS_TO_SLEEP; param_thread->reg_to_write = 0x0000050; /**** POPULATE param_thread *****/ param_thread->th1 = 500000000.0 * 4; param_thread->th2 = 0; param_thread->th3 = 0; param_thread->th4 = 0; /**** END POPULATE param_thread *****/ if(pthread_create(&governor_thread,NULL,governor_function,param_thread)<0) { printf("pthread_create error for thread 1\n"); exit(1); } // Call pthread_join if we want to wait for the termination of governor_thread. Else comment it int retcode = pthread_join(governor_thread,NULL); closeDescriptor(&nf2); free(param_thread); return 0; }
int main(int argc, char *argv[]) { unsigned val; nf2.device_name = DEFAULT_IFACE; if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } print(); closeDescriptor(&nf2); return 0; }
int main(int argc, char *argv[]) { nf2.device_name = DEFAULT_IFACE; processArgs(argc, argv); if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } nf2_read_info(&nf2); display_info(&nf2); closeDescriptor(&nf2); return 0; }
/* 销毁init里面的线程读写锁 */ void destroy(struct sr_instance* sr) { router_state* rs = sr->interface_subsystem; /** DESTROY LOCKS **/ if (pthread_mutex_destroy(rs->write_lock) != 0) { perror("Lock destroy error"); } free(rs->write_lock); if (pthread_rwlock_destroy(rs->arp_cache_lock) != 0) { perror("Lock destroy error"); } free(rs->arp_cache_lock); if (pthread_rwlock_destroy(rs->arp_queue_lock) != 0) { perror("Lock destroy error"); } free(rs->arp_queue_lock); if (pthread_rwlock_destroy(rs->if_list_lock) != 0) { perror("Lock destroy error"); } free(rs->if_list_lock); if (pthread_rwlock_destroy(rs->rtable_lock) != 0) { perror("Lock destroy error"); } free(rs->rtable_lock); // --- CCDN lock if (pthread_rwlock_destroy(rs->ctable_lock) != 0) { perror("Lock destroy error"); } free(rs->ctable_lock); if (pthread_rwlock_destroy(rs->cli_commands_lock) != 0) { perror("Lock destroy error"); } free(rs->cli_commands_lock); if (pthread_mutex_destroy(rs->nat_table_mutex) != 0) { perror("Lock destroy error"); } free(rs->nat_table_mutex); if (pthread_cond_destroy(rs->nat_table_cond) != 0) { perror("Cond destroy error"); } free(rs->nat_table_cond); /* destroy dijkstra stuff */ if (pthread_mutex_destroy(rs->dijkstra_mutex) != 0) { perror("Mutex destroy error"); } free(rs->dijkstra_mutex); if (pthread_cond_destroy(rs->dijkstra_cond) != 0) { perror("Cond destroy error"); } free(rs->dijkstra_cond); /* destroy www stuff */ if (pthread_mutex_destroy(rs->www_mutex) != 0) { perror("Mutex destroy error"); } free(rs->www_mutex); if (pthread_cond_destroy(rs->www_cond) != 0) { perror("Cond destroy error"); } free(rs->www_cond); #ifdef _CPUMODE_ closeDescriptor(&(rs->netfpga)); #endif if (pthread_mutex_destroy(rs->local_ip_filter_list_mutex) != 0) { perror("Mutex destroy error"); } else { free(rs->local_ip_filter_list_mutex); } /** TODO: Free the lists **/ }
int main(int argc, char *argv[]) { nf2.device_name = DEFAULT_IFACE; /* Default */ sprintf(ip,"127.0.0.1"); porta = 7777; processArgs(argc, argv); // Open the interface if possible if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } /* SOCKET */ int fd; if((fd = socket(AF_INET,SOCK_DGRAM,0)) < 0) { printf("ERROR! socket\n"); goto exit_thread; } /* THREAD - dumpCount() */ int rc; pthread_t thread; rc = pthread_create(&thread,NULL,dumpCounts,NULL); if(rc) { printf("ERROR! Return code from pthread_create is %d\n", rc); goto exit_no_thread; } bzero((void*)&servidor, sizeof(servidor)); servidor.sin_family = AF_INET; inet_pton(AF_INET,ip,(void*)&(servidor.sin_addr.s_addr)); servidor.sin_port = htons(porta); int rb; if((rb = bind(fd, (struct sockaddr *)&servidor, sizeof(servidor))) < 0) { printf("ERROR! bind\n"); goto exit_thread; } printf("listener: waiting to recvfrom\n"); char buf[MAXBUFLEN]; int numbytes; struct sockaddr_storage their_addr; socklen_t addr_len; while(1) { if((numbytes = recvfrom(fd, buf, MAXBUFLEN-1, 0, (struct sockaddr *)&their_addr, &addr_len)) == -1) { printf("ERROR! recvfrom\n"); goto exit_thread; } buf[numbytes] = '\0'; printf("DADOS DO PACOTE: \n%s\n\n",buf); } exit_thread: pthread_exit(NULL); exit_no_thread: closeDescriptor(&nf2); close(fd); return 0; }
int main() { unsigned val; int i; uint32_t queue_addr_offset = OQ_QUEUE_1_ADDR_LO_REG - OQ_QUEUE_0_ADDR_LO_REG; uint32_t curr_addr = 0; uint32_t rx_queue_size = (MEM_SIZE - 4*XMIT_QUEUE_SIZE)/8; uint32_t src_port = 0, dst_port = 0x100; uint32_t word_len = 0, len = 0x100; uint32_t queue_base_addr[] = {0,0,0,0}; char *data; uint32_t data_len, rate_limit_offset; uint32_t pointer = 0, pkt_pointer = 0; uint32_t drop; nf2.device_name = DEFAULT_IFACE; if (check_iface(&nf2)) exit(1); if (openDescriptor(&nf2)) exit(1); // Disable the output queues by writing 0x0 to the enable register writeReg(&nf2, PKT_GEN_CTRL_ENABLE_REG, 0x00); //generate the data we want to send init_data(&det); innitialize_generator_packet(&state, &det); // Disable output queues // Note: 3 queues per port -- rx, tx and tx-during-setup for (i = 0; i < 3 * NUM_PORTS; i++) { writeReg (&nf2, (OQ_QUEUE_0_CTRL_REG + i*queue_addr_offset), 0x00); } //Set queue sizes thourght the relevant registers for (i = 0; i<NUM_PORTS; i++) { //set queue sizes for tx-during-setup writeReg (&nf2, (OQ_QUEUE_0_ADDR_LO_REG + (i*2)*queue_addr_offset), curr_addr); writeReg (&nf2, (OQ_QUEUE_0_ADDR_HI_REG + (i*2)*queue_addr_offset), curr_addr + XMIT_QUEUE_SIZE - 1); writeReg (&nf2, (OQ_QUEUE_0_CTRL_REG + (i*2)*queue_addr_offset), 0x02); curr_addr += XMIT_QUEUE_SIZE; //Set queue sizes for RX queues writeReg (&nf2,OQ_QUEUE_0_ADDR_LO_REG + (i*2+1)*queue_addr_offset, curr_addr); writeReg (&nf2,OQ_QUEUE_0_ADDR_HI_REG + (i*2+1)*queue_addr_offset, curr_addr+rx_queue_size-1); writeReg (&nf2,OQ_QUEUE_0_CTRL_REG + (i*2+1)*queue_addr_offset, 0x02); curr_addr += rx_queue_size; } for (i = 0; i < NUM_PORTS; i++) { //Set queue sizes for TX queues writeReg (&nf2, OQ_QUEUE_0_ADDR_LO_REG + (i + 2*NUM_PORTS)*queue_addr_offset, curr_addr); writeReg (&nf2, OQ_QUEUE_0_ADDR_HI_REG + (i + 2*NUM_PORTS)*queue_addr_offset, curr_addr + ((i == 3)? det.pkt_size + ceil(det.pkt_size/8) + 1:1) - 1); writeReg (&nf2,OQ_QUEUE_0_CTRL_REG + (i+2*NUM_PORTS)*queue_addr_offset, 0x02); queue_base_addr[i] = curr_addr; curr_addr += ((i == 3)? det.pkt_size + ceil(det.pkt_size/8) + 1:1); //$queue_base_addr[$i] = $curr_addr; //$curr_addr += $queue_size; } //data + netfpga packet length + 1 byte for the ctrl part for each word data_len = state.data_len + 9 + ceil((float)state.data_len/8); data = malloc(data_len); bzero(data, data_len); pointer = 0; pkt_pointer = 0; //append netfpga header data[pointer] = IO_QUEUE_STAGE_NUM; pointer++; *(uint16_t *)(data + pointer ) = 0x0; pointer+=2; *(uint16_t *)(data + pointer ) = (uint16_t)ceil((float)state.data_len/8); pointer+=2; *(uint16_t *)(data + pointer ) = (uint16_t)(0x100 << 3); pointer+=2; *(uint16_t *)(data + pointer ) = (uint16_t)state.data_len; pointer+=2; printf("size: %d %d output: %d\n", (uint16_t)ceil((float)state.data_len/8), state.data_len, (uint16_t)(0x100 << 3)); //put data queue_addr_offset = OQ_QUEUE_GROUP_INST_OFFSET; for(i = 0; i < floor((float)state.data_len/8); i++) { data[pointer] = 0x0; pointer++; memcpy(data+pointer, state.data + pkt_pointer, 8); pkt_pointer += 8; pointer += 8; } data[pointer] = state.data_len - pkt_pointer; pointer++; memcpy(data+pointer, state.data + pkt_pointer, state.data_len - pkt_pointer); pointer+= state.data_len - pkt_pointer; uint32_t sram_addr = SRAM_BASE_ADDR + queue_base_addr[3]*16; //finally copy data on the SRAM for (i = 0; i < data_len; i+=3) { writeReg (&nf2,sram_addr + 0x0, *((uint32_t *)(data + 4*i))); writeReg (&nf2,sram_addr + 0x4, *((uint32_t *)(data + 4*(i + 1)))); writeReg (&nf2,sram_addr + 0x8, *((uint32_t *)(data + 4*(i + 2)))); int j; if (4*i < 64) { for (j = 4*i; (j < 4*i+16); j+=4) { printf("%02x%02x%02x%02x ", (uint8_t)data[j], (uint8_t)data[j+1], (uint8_t)data[j+2], (uint8_t)data[j+3]); } printf("\n"); } sram_addr += 12; } //ff 0000 af00 0008 7805 0000 15 // Set the rate limiter for CPU queues /* for (i = 0; i < 4; i++) { */ /* rate_limiter_set(i * 2 + 1, 200000); */ /* } */ queue_addr_offset = OQ_QUEUE_GROUP_INST_OFFSET; // Set the number of iterations for the queues with pcap files for (i = 0; i < NUM_PORTS; i++) { // rate_limiter_disable($i * 2); rate_limit_offset = RATE_LIMIT_1_CTRL_REG - RATE_LIMIT_0_CTRL_REG; //disable repetition writeReg(&nf2, OQ_QUEUE_0_CTRL_REG + (i + 2 * NUM_PORTS) * queue_addr_offset, 0x0); // writeReg (&nf2, RATE_LIMIT_0_CTRL_REG + 2 * i * rate_limit_offset, 0x0); // disable rate limit on CPU queues writeReg (&nf2, RATE_LIMIT_0_CTRL_REG + (2*i + 1) * rate_limit_offset, 0x0); } //set queue 3 to repeat once writeReg(&nf2, OQ_QUEUE_0_CTRL_REG + (3 + 2 * NUM_PORTS) * queue_addr_offset, 0x1); writeReg(&nf2, OQ_QUEUE_0_MAX_ITER_REG + (3 + 2 * NUM_PORTS) * queue_addr_offset, 1); //Enable the packet generator hardware to send the packets drop = 0; /* for (i = 0; i < NUM_PORTS; i++) { */ /* drop = drop | (1 << i); */ /* drop = drop << 8; */ /* } */ printf("drop 0x%X...\n", drop | 0xF); //packet_generator_enable (drop | 0xF); writeReg(&nf2, PKT_GEN_CTRL_ENABLE_REG, drop | 0xF); sleep(10); //Finish up writeReg(&nf2, PKT_GEN_CTRL_ENABLE_REG, 0x0); for (i = 0; i < 1024; i++) { // reset_delay(); writeReg(&nf2, DELAY_RESET_REG, 1); } //display_xmit_metrics(); printf("Transmit statistics:\n"); printf("====================\n\n"); for (i = 0; i < NUM_PORTS; i++) { uint32_t pkt_cnt, iter_cnt; readReg(&nf2, OQ_QUEUE_0_NUM_PKTS_REMOVED_REG + (i + 8) * queue_addr_offset, &pkt_cnt); readReg(&nf2, OQ_QUEUE_0_CURR_ITER_REG + (i + 8) * queue_addr_offset, &iter_cnt); printf("%d:\n", i + 8); printf("\tPackets: %u\n", pkt_cnt); printf("\tCompleted iterations: %u\n", iter_cnt); } printf("\n\n"); //display_capture_metrics(); printf("sending packet completed..."); closeDescriptor(&nf2); printf("Test successful\n"); }
/* Checks for commandline args, intializes globals, then begins code download. */ int download_very_fast(int frequency) { nf2.device_name = DEFAULT_IFACE; struct in_addr ip[32], mask[32], gw[32], gw_arp[32], ip_filter[32]; unsigned int mac_hi[32]; unsigned int mac_lo[32]; unsigned int mac0_hi,mac0_lo; unsigned int mac1_hi,mac1_lo; unsigned int mac2_hi,mac2_lo; unsigned int mac3_hi,mac3_lo; /*if(argc<2) { printf("run <command> <0/1> (0 down; 1 up)\n"); exit(1); }*/ freq = frequency; if(freq!=0 && freq!=1) { printf("argument must be either 0 or 1!!!\n"); exit(1); } if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } int i; char iface; unsigned int port[32]; readReg(&nf2,ROUTER_OP_LUT_MAC_0_HI_REG,&mac0_hi); readReg(&nf2,ROUTER_OP_LUT_MAC_1_HI_REG,&mac1_hi); readReg(&nf2,ROUTER_OP_LUT_MAC_2_HI_REG,&mac2_hi); readReg(&nf2,ROUTER_OP_LUT_MAC_3_HI_REG,&mac3_hi); readReg(&nf2,ROUTER_OP_LUT_MAC_0_LO_REG,&mac0_lo); readReg(&nf2,ROUTER_OP_LUT_MAC_1_LO_REG,&mac1_lo); readReg(&nf2,ROUTER_OP_LUT_MAC_2_LO_REG,&mac2_lo); readReg(&nf2,ROUTER_OP_LUT_MAC_3_LO_REG,&mac3_lo); for(i=0; i<32;i++) { bzero(&ip_filter[i], sizeof(struct in_addr)); writeReg(&nf2, ROUTER_OP_LUT_DST_IP_FILTER_TABLE_RD_ADDR_REG, i); readReg(&nf2, ROUTER_OP_LUT_DST_IP_FILTER_TABLE_ENTRY_IP_REG, &ip_filter[i].s_addr); bzero(&gw_arp[i], sizeof(struct in_addr)); /* write the row number */ writeReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_RD_ADDR_REG, i); /* read the four-touple (mac hi, mac lo, gw, num of misses) */ readReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_HI_REG, &mac_hi[i]); readReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_LO_REG, &mac_lo[i]); readReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_NEXT_HOP_IP_REG, &gw_arp[i].s_addr); bzero(&ip[i], sizeof(struct in_addr)); bzero(&mask[i], sizeof(struct in_addr)); bzero(&gw[i], sizeof(struct in_addr)); /* write the row number */ writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_RD_ADDR_REG, i); /* read the four-tuple (ip, gw, mask, iface) from the hw registers */ readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_IP_REG, &ip[i].s_addr); readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_MASK_REG, &mask[i].s_addr); readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_NEXT_HOP_IP_REG, &gw[i].s_addr); readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_OUTPUT_PORT_REG, &port[i]); } ResetDevice(); writeReg(&nf2,ROUTER_OP_LUT_MAC_0_HI_REG,mac0_hi); writeReg(&nf2,ROUTER_OP_LUT_MAC_1_HI_REG,mac1_hi); writeReg(&nf2,ROUTER_OP_LUT_MAC_2_HI_REG,mac2_hi); writeReg(&nf2,ROUTER_OP_LUT_MAC_3_HI_REG,mac3_hi); writeReg(&nf2,ROUTER_OP_LUT_MAC_0_LO_REG,mac0_lo); writeReg(&nf2,ROUTER_OP_LUT_MAC_1_LO_REG,mac1_lo); writeReg(&nf2,ROUTER_OP_LUT_MAC_2_LO_REG,mac2_lo); writeReg(&nf2,ROUTER_OP_LUT_MAC_3_LO_REG,mac3_lo); for(i=0; i<32;i++) { writeReg(&nf2, ROUTER_OP_LUT_DST_IP_FILTER_TABLE_ENTRY_IP_REG, ip_filter[i].s_addr); writeReg(&nf2, ROUTER_OP_LUT_DST_IP_FILTER_TABLE_WR_ADDR_REG, i); /* read the four-tuple (ip, gw, mask, iface) from the hw registers */ writeReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_HI_REG, mac_hi[i]); writeReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_LO_REG, mac_lo[i]); writeReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_NEXT_HOP_IP_REG, gw_arp[i].s_addr); /* write the row number */ writeReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_WR_ADDR_REG, i); /* read the four-tuple (ip, gw, mask, iface) from the hw registers */ writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_IP_REG, ip[i].s_addr); writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_MASK_REG, mask[i].s_addr); writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_NEXT_HOP_IP_REG, gw[i].s_addr); writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_OUTPUT_PORT_REG, port[i]); /* write the row number */ writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_WR_ADDR_REG, i); } /* wait until the resets have been completed */ usleep(1); closeDescriptor(&nf2); return SUCCESS; }