void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
new_brownout = new_target - new_brownout;
cur_target = readl(&power_regs->hw_power_vdddctrl);
cur_target &= POWER_VDDDCTRL_TRG_MASK;
cur_target *= 25; /* 25 mV step*/
cur_target += 800; /* 800 mV lowest */
powered_by_linreg = mx28_get_vddd_power_source_off();
if (new_target > cur_target) {
if (powered_by_linreg) {
bo_int = readl(&power_regs->hw_power_vdddctrl);
clrbits_le32(&power_regs->hw_power_vdddctrl,
POWER_CTRL_ENIRQ_VDDD_BO);
}
setbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_BO_OFFSET_MASK);
do {
if (new_target - cur_target > 100)
diff = cur_target + 100;
else
diff = new_target;
diff -= 800;
diff /= 25;
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_TRG_MASK, diff);
if (powered_by_linreg ||
(readl(&power_regs->hw_power_sts) &
POWER_STS_VDD5V_GT_VDDIO))
early_delay(1500);
else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK))
;
}
cur_target = readl(&power_regs->hw_power_vdddctrl);
cur_target &= POWER_VDDDCTRL_TRG_MASK;
cur_target *= 25; /* 25 mV step*/
cur_target += 800; /* 800 mV lowest */
} while (new_target > cur_target);
if (powered_by_linreg) {
writel(POWER_CTRL_VDDD_BO_IRQ,
&power_regs->hw_power_ctrl_clr);
if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
setbits_le32(&power_regs->hw_power_vdddctrl,
POWER_CTRL_ENIRQ_VDDD_BO);
}
} else {
do {
if (cur_target - new_target > 100)
diff = cur_target - 100;
else
diff = new_target;
diff -= 800;
diff /= 25;
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_TRG_MASK, diff);
if (powered_by_linreg ||
(readl(&power_regs->hw_power_sts) &
POWER_STS_VDD5V_GT_VDDIO))
early_delay(1500);
else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK))
;
}
cur_target = readl(&power_regs->hw_power_vdddctrl);
cur_target &= POWER_VDDDCTRL_TRG_MASK;
cur_target *= 25; /* 25 mV step*/
cur_target += 800; /* 800 mV lowest */
} while (new_target < cur_target);
}
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_BO_OFFSET_MASK,
new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
}
void system_clock_init(struct mem_timings *mem,
struct arm_clk_ratios *arm_clk_ratio)
{
u32 val, tmp;
/* Turn on the MCT as early as possible. */
exynos_mct->g_tcon |= (1 << 8);
clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK);
do {
val = readl(&exynos_clock->mux_stat_cpu);
} while ((val | MUX_APLL_SEL_MASK) != val);
clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK);
do {
val = readl(&exynos_clock->mux_stat_core1);
} while ((val | MUX_MPLL_SEL_MASK) != val);
clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK);
clrbits_le32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK);
clrbits_le32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK);
clrbits_le32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK);
tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
| MUX_GPLL_SEL_MASK;
do {
val = readl(&exynos_clock->mux_stat_top2);
} while ((val | tmp) != val);
clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK);
do {
val = readl(&exynos_clock->mux_stat_cdrex);
} while ((val | MUX_BPLL_SEL_MASK) != val);
/* PLL locktime */
writel(APLL_LOCK_VAL, &exynos_clock->apll_lock);
writel(MPLL_LOCK_VAL, &exynos_clock->mpll_lock);
writel(BPLL_LOCK_VAL, &exynos_clock->bpll_lock);
writel(CPLL_LOCK_VAL, &exynos_clock->cpll_lock);
writel(GPLL_LOCK_VAL, &exynos_clock->gpll_lock);
writel(EPLL_LOCK_VAL, &exynos_clock->epll_lock);
writel(VPLL_LOCK_VAL, &exynos_clock->vpll_lock);
writel(CLK_REG_DISABLE, &exynos_clock->pll_div2_sel);
writel(MUX_HPM_SEL_MASK, &exynos_clock->src_cpu);
do {
val = readl(&exynos_clock->mux_stat_cpu);
} while ((val | HPM_SEL_SCLK_MPLL) != val);
val = arm_clk_ratio->arm2_ratio << 28
| arm_clk_ratio->apll_ratio << 24
| arm_clk_ratio->pclk_dbg_ratio << 20
| arm_clk_ratio->atb_ratio << 16
| arm_clk_ratio->periph_ratio << 12
| arm_clk_ratio->acp_ratio << 8
| arm_clk_ratio->cpud_ratio << 4
| arm_clk_ratio->arm_ratio;
writel(val, &exynos_clock->div_cpu0);
do {
val = readl(&exynos_clock->div_stat_cpu0);
} while (0 != val);
writel(CLK_DIV_CPU1_VAL, &exynos_clock->div_cpu1);
do {
val = readl(&exynos_clock->div_stat_cpu1);
} while (0 != val);
/* switch A15 clock source to OSC clock before changing APLL */
clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT);
/* Set APLL */
writel(APLL_CON1_VAL, &exynos_clock->apll_con1);
val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
arm_clk_ratio->apll_sdiv);
writel(val, &exynos_clock->apll_con0);
while ((readl(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0)
;
/* now it is safe to switch to APLL */
setbits_le32(&exynos_clock->src_cpu, APLL_FOUT);
/* Set MPLL */
writel(MPLL_CON1_VAL, &exynos_clock->mpll_con1);
val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
writel(val, &exynos_clock->mpll_con0);
while ((readl(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0)
;
/*
* Configure MUX_MPLL_FOUT to choose the direct clock source
* path and avoid the fixed DIV/2 block to save power
*/
setbits_le32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL);
/* Set BPLL */
if (mem->use_bpll) {
writel(BPLL_CON1_VAL, &exynos_clock->bpll_con1);
val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
writel(val, &exynos_clock->bpll_con0);
while ((readl(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0)
;
setbits_le32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL);
}
/* Set CPLL */
writel(CPLL_CON1_VAL, &exynos_clock->cpll_con1);
val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
writel(val, &exynos_clock->cpll_con0);
while ((readl(&exynos_clock->cpll_con0) & CPLL_CON0_LOCKED) == 0)
;
/* Set GPLL */
writel(GPLL_CON1_VAL, &exynos_clock->gpll_con1);
val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
writel(val, &exynos_clock->gpll_con0);
while ((readl(&exynos_clock->gpll_con0) & GPLL_CON0_LOCKED) == 0)
;
/* Set EPLL */
writel(EPLL_CON2_VAL, &exynos_clock->epll_con2);
writel(EPLL_CON1_VAL, &exynos_clock->epll_con1);
val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
writel(val, &exynos_clock->epll_con0);
while ((readl(&exynos_clock->epll_con0) & EPLL_CON0_LOCKED) == 0)
;
/* Set VPLL */
writel(VPLL_CON2_VAL, &exynos_clock->vpll_con2);
writel(VPLL_CON1_VAL, &exynos_clock->vpll_con1);
val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
writel(val, &exynos_clock->vpll_con0);
while ((readl(&exynos_clock->vpll_con0) & VPLL_CON0_LOCKED) == 0)
;
writel(CLK_SRC_CORE0_VAL, &exynos_clock->src_core0);
writel(CLK_DIV_CORE0_VAL, &exynos_clock->div_core0);
while (readl(&exynos_clock->div_stat_core0) != 0)
;
writel(CLK_DIV_CORE1_VAL, &exynos_clock->div_core1);
while (readl(&exynos_clock->div_stat_core1) != 0)
;
writel(CLK_DIV_SYSRGT_VAL, &exynos_clock->div_sysrgt);
while (readl(&exynos_clock->div_stat_sysrgt) != 0)
;
writel(CLK_DIV_ACP_VAL, &exynos_clock->div_acp);
while (readl(&exynos_clock->div_stat_acp) != 0)
;
writel(CLK_DIV_SYSLFT_VAL, &exynos_clock->div_syslft);
while (readl(&exynos_clock->div_stat_syslft) != 0)
;
writel(CLK_SRC_TOP0_VAL, &exynos_clock->src_top0);
writel(CLK_SRC_TOP1_VAL, &exynos_clock->src_top1);
writel(TOP2_VAL, &exynos_clock->src_top2);
writel(CLK_SRC_TOP3_VAL, &exynos_clock->src_top3);
writel(CLK_DIV_TOP0_VAL, &exynos_clock->div_top0);
while (readl(&exynos_clock->div_stat_top0))
;
writel(CLK_DIV_TOP1_VAL, &exynos_clock->div_top1);
while (readl(&exynos_clock->div_stat_top1))
;
writel(CLK_SRC_LEX_VAL, &exynos_clock->src_lex);
while (1) {
val = readl(&exynos_clock->mux_stat_lex);
if (val == (val | 1))
break;
}
writel(CLK_DIV_LEX_VAL, &exynos_clock->div_lex);
while (readl(&exynos_clock->div_stat_lex))
;
writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x);
while (readl(&exynos_clock->div_stat_r0x))
;
writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x);
while (readl(&exynos_clock->div_stat_r0x))
;
writel(CLK_DIV_R1X_VAL, &exynos_clock->div_r1x);
while (readl(&exynos_clock->div_stat_r1x))
;
if (mem->use_bpll) {
writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL |
MUX_MCLK_DPHY_SEL, &exynos_clock->src_cdrex);
} else {
writel(CLK_REG_DISABLE, &exynos_clock->src_cdrex);
}
writel(CLK_DIV_CDREX_VAL, &exynos_clock->div_cdrex);
while (readl(&exynos_clock->div_stat_cdrex))
;
val = readl(&exynos_clock->src_cpu);
val |= CLK_SRC_CPU_VAL;
writel(val, &exynos_clock->src_cpu);
val = readl(&exynos_clock->src_top2);
val |= CLK_SRC_TOP2_VAL;
writel(val, &exynos_clock->src_top2);
val = readl(&exynos_clock->src_core1);
val |= CLK_SRC_CORE1_VAL;
writel(val, &exynos_clock->src_core1);
writel(CLK_SRC_FSYS0_VAL, &exynos_clock->src_fsys);
writel(CLK_DIV_FSYS0_VAL, &exynos_clock->div_fsys0);
while (readl(&exynos_clock->div_stat_fsys0))
;
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cpu);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_core);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_acp);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_top);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_lex);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r0x);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r1x);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cdrex);
writel(CLK_SRC_PERIC0_VAL, &exynos_clock->src_peric0);
writel(CLK_DIV_PERIC0_VAL, &exynos_clock->div_peric0);
writel(CLK_SRC_PERIC1_VAL, &exynos_clock->src_peric1);
writel(CLK_DIV_PERIC1_VAL, &exynos_clock->div_peric1);
writel(CLK_DIV_PERIC2_VAL, &exynos_clock->div_peric2);
writel(SCLK_SRC_ISP_VAL, &exynos_clock->sclk_src_isp);
writel(SCLK_DIV_ISP_VAL, &exynos_clock->sclk_div_isp);
writel(CLK_DIV_ISP0_VAL, &exynos_clock->div_isp0);
writel(CLK_DIV_ISP1_VAL, &exynos_clock->div_isp1);
writel(CLK_DIV_ISP2_VAL, &exynos_clock->div_isp2);
/* FIMD1 SRC CLK SELECTION */
writel(CLK_SRC_DISP1_0_VAL, &exynos_clock->src_disp1_0);
val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
| MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
| MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
| MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
writel(val, &exynos_clock->div_fsys2);
}
static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
{
clrbits_le32(®s->func_en_1, SW_FUNC_EN_N);
}
static void read_write_byte(struct s3c24x0_i2c *i2c)
{
clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
}
/*
* scan_mgr_io_scan_chain_prg
* Program HPS IO Scan Chain
*/
unsigned long
scan_mgr_io_scan_chain_prg(
IOScanChainSelect io_scan_chain_id,
uint32_t io_scan_chain_len_in_bits,
const unsigned long *iocsr_scan_chain)
{
uint16_t tdi_tdo_header;
uint32_t io_program_iter;
uint32_t io_scan_chain_data_residual;
uint32_t residual;
uint32_t i;
uint32_t index = 0;
/*
* Check if IO bank is in frozen state before proceed to program IO
* scan chain.
* Note: IO scan chain ID is 1:1 mapping to freeze channel ID
*/
DEBUG_MEMORY
if (sys_mgr_frzctrl_frzchn_is_frozen(io_scan_chain_id)) {
/* De-assert reinit if the IO scan chain is intended for HIO */
if (IO_SCAN_CHAIN_3 == io_scan_chain_id) {
DEBUG_MEMORY
clrbits_le32((SOCFPGA_SYSMGR_ADDRESS+
SYSMGR_FRZCTRL_HIOCTRL_ADDRESS),
SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
} /* if (HIO) */
/*
* Check if the scan chain engine is inactive and the
* WFIFO is empty before enabling the IO scan chain
*/
if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
!= scan_mgr_io_scan_chain_engine_is_idle(
MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
DEBUG_MEMORY
return 1;
}
/*
* Enable IO Scan chain based on scan chain id
* Note: only one chain can be enabled at a time
*/
setbits_le32((SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_EN_ADDRESS),
1 << io_scan_chain_id);
/*
* Calculate number of iteration needed for
* full 128-bit (4 x32-bits) bits shifting.
* Each TDI_TDO packet can shift in maximum 128-bits
*/
io_program_iter
= io_scan_chain_len_in_bits >>
IO_SCAN_CHAIN_128BIT_SHIFT;
io_scan_chain_data_residual
= io_scan_chain_len_in_bits &
IO_SCAN_CHAIN_128BIT_MASK;
/*
* Construct TDI_TDO packet for
* 128-bit IO scan chain (2 bytes)
*/
tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE
| (TDI_TDO_MAX_PAYLOAD <<
TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
/* Program IO scan chain in 128-bit iteration */
DEBUG_MEMORY
for (i = 0; i < io_program_iter; i++) {
/* write TDI_TDO packet header to scan manager */
writel(tdi_tdo_header,
(SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_FIFODOUBLEBYTE_ADDRESS));
/* calculate array index */
index = i * 4;
/*
* write 4 successive 32-bit IO scan
* chain data into WFIFO
*/
writel(iocsr_scan_chain[index],
(SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_FIFOQUADBYTE_ADDRESS));
writel(iocsr_scan_chain[index + 1],
(SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_FIFOQUADBYTE_ADDRESS));
writel(iocsr_scan_chain[index + 2],
(SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_FIFOQUADBYTE_ADDRESS));
writel(iocsr_scan_chain[index + 3],
(SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_FIFOQUADBYTE_ADDRESS));
/*
* Check if the scan chain engine has completed the
* IO scan chain data shifting
*/
if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
!= scan_mgr_io_scan_chain_engine_is_idle(
MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
DEBUG_MEMORY
/* Disable IO Scan chain when error detected */
clrbits_le32((SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_EN_ADDRESS),
1 << io_scan_chain_id);
return 1;
}
}
/* Calculate array index for final TDI_TDO packet */
index = io_program_iter * 4;
/* Final TDI_TDO packet if any */
DEBUG_MEMORY
if (0 != io_scan_chain_data_residual) {
/*
* Calculate number of quad bytes FIFO write
* needed for the final TDI_TDO packet
*/
io_program_iter
= io_scan_chain_data_residual >>
IO_SCAN_CHAIN_32BIT_SHIFT;
/*
* Construct TDI_TDO packet for remaining IO
* scan chain (2 bytes)
*/
tdi_tdo_header
= TDI_TDO_HEADER_FIRST_BYTE |
((io_scan_chain_data_residual - 1)
<< TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
/*
* Program the last part of IO scan chain
* write TDI_TDO packet header (2 bytes) to
* scan manager
*/
writel(tdi_tdo_header,
(SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_FIFODOUBLEBYTE_ADDRESS));
DEBUG_MEMORY
for (i = 0; i < io_program_iter; i++) {
/*
* write remaining scan chain data into scan
* manager WFIFO with 4 bytes write
*/
writel(iocsr_scan_chain[index + i],
(SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_FIFOQUADBYTE_ADDRESS));
}
index += io_program_iter;
residual = io_scan_chain_data_residual &
IO_SCAN_CHAIN_32BIT_MASK;
if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) {
/*
* write the last 4B scan chain data
* into scan manager WFIFO
*/
DEBUG_MEMORY
writel(iocsr_scan_chain[index],
(SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_FIFOQUADBYTE_ADDRESS));
} else {
/*
* write the remaining 1 - 3 bytes scan chain
* data into scan manager WFIFO byte by byte
* to prevent JTAG engine shifting unused data
* from the FIFO and mistaken the data as a
* valid command (even though unused bits are
* set to 0, but just to prevent hardware
* glitch)
*/
DEBUG_MEMORY
for (i = 0; i < residual; i += 8) {
writel(
((iocsr_scan_chain[index] >> i)
& IO_SCAN_CHAIN_BYTE_MASK),
(SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_FIFOSINGLEBYTE_ADDRESS)
);
}
}
/*
* Check if the scan chain engine has completed the
* IO scan chain data shifting
*/
if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
!= scan_mgr_io_scan_chain_engine_is_idle(
MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
DEBUG_MEMORY
/* Disable IO Scan chain when error detected */
clrbits_le32((SOCFPGA_SCANMGR_ADDRESS +
SCANMGR_EN_ADDRESS),
1 << io_scan_chain_id);
return 1;
}
} /* if (io_scan_chain_data_residual) */
static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
unsigned int tmpdout, tmpdin;
int tm, isread = 0;
debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
if (flags & SPI_XFER_BEGIN)
_spi_cs_activate(reg);
/*
* handle data in 8-bit chunks
* TBD: 2byte xfer mode to be enabled
*/
clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
while (bitlen > 4) {
debug("loopstart bitlen %d\n", bitlen);
tmpdout = 0;
/* Shift data so it's msb-justified */
if (dout)
tmpdout = *(u32 *)dout & 0xff;
clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ);
writel(tmpdout, ®->dout); /* Write the data out */
debug("*** spi_xfer: ... %08x written, bitlen %d\n",
tmpdout, bitlen);
/*
* Wait for SPI transmit to get out
* or time out (1 second = 1000 ms)
* The NE event must be read and cleared first
*/
for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) {
isread = 1;
tmpdin = readl(®->din);
debug("spi_xfer: din %p..%08x read\n",
din, tmpdin);
if (din) {
*((u8 *)din) = (u8)tmpdin;
din += 1;
}
if (dout)
dout += 1;
bitlen -= 8;
}
if (isread)
break;
}
if (tm >= KWSPI_TIMEOUT)
printf("*** spi_xfer: Time out during SPI transfer\n");
debug("loopend bitlen %d\n", bitlen);
}
if (flags & SPI_XFER_END)
_spi_cs_deactivate(reg);
return 0;
}
static void mxs_power_init_4p2_regulator(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
&power_regs->hw_power_5vctrl_clr);
clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
/* Power up the 4p2 rail and logic/control */
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_clr);
/*
* Start charging up the 4p2 capacitor. We ramp of this charge
* gradually to avoid large inrush current from the 5V cable which can
* cause transients/problems
*/
mxs_enable_4p2_dcdc_input(0);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
/*
* If we arrived here, we were unable to recover from mx23 chip
* errata 5837. 4P2 is disabled and sufficient battery power is
* not present. Exiting to not enable DCDC power during 5V
* connected state.
*/
clrbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_ENABLE_DCDC);
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_set);
hang();
}
/*
* Here we set the 4p2 brownout level to something very close to 4.2V.
* We then check the brownout status. If the brownout status is false,
* the voltage is already close to the target voltage of 4.2V so we
* can go ahead and set the 4P2 current limit to our max target limit.
* If the brownout status is true, we need to ramp us the current limit
* so that we don't cause large inrush current issues. We step up the
* current limit until the brownout status is false or until we've
* reached our maximum defined 4p2 current limit.
*/
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK,
22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
setbits_le32(&power_regs->hw_power_5vctrl,
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
} else {
tmp = (readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
while (tmp < 0x3f) {
if (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DCDC_4P2_BO)) {
tmp = readl(&power_regs->hw_power_5vctrl);
tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
early_delay(100);
writel(tmp, &power_regs->hw_power_5vctrl);
break;
} else {
tmp++;
tmp2 = readl(&power_regs->hw_power_5vctrl);
tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
tmp2 |= tmp <<
POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
writel(tmp2, &power_regs->hw_power_5vctrl);
early_delay(100);
}
}
}
clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
static void sdio_pwr_off(unsigned port)
{
setbits_le32(P_PREG_CGPIO_O,(1<<12));
clrbits_le32(P_PREG_CGPIO_EN_N,(1<<12));
}
static void hdmi_tx_set_hdmi_5v(void)
{
/*Power on VCC_5V for HDMI_5V*/
clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
}
void lowlevel_init(void* cur,void * target)
{
int i;
#if 0
if(cur != target) //r0!=r1
{
//running from spi
// take me as a spi rom boot mode
romboot_info->por_cfg = POR_INTL_SPI |
(READ_CBUS_REG(ASSIST_POR_CONFIG)&(~POR_INTL_CFG_MASK));
romboot_info->boot_id = 0;//boot from spi
/// Release pull up registers .
}
#endif
//gpiob_8
clrbits_le32(P_PREG_GGPIO_O, 1<<16);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<16);
//gpiob_5
clrbits_le32(P_PREG_GGPIO_O, 1<<13);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<13);
//writel((1<<22)|100000,P_WATCHDOG_TC);//enable Watchdog 1 seconds
//Adjust 1us timer base
//clrbits_le32(P_PREG_FGPIO_O, 1<<21);
//mute
// setbits_le32(P_PREG_GGPIO_O, 1<<5);
// clrbits_le32(P_PREG_GGPIO_EN_N, 1<<5);
// //vcc_12v/24v power down GPIOX_70
// setbits_le32(P_PREG_GGPIO_O, 1<<6);
// clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
// bl
// setbits_le32(P_PREG_FGPIO_O, 1<<21);
// clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);
//Wr(REG_LVDS_PHY_CNTL4, 0);//LVDS_MDR_PU
//clrbits_le32(P_PREG_GGPIO_O, 1<<6);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
/*
Select TimerE 1 us base
*/
clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);
if(1)
{
writel(0,P_WATCHDOG_TC);//disable Watchdog
//while(1)
{
__udelay(50000);
}
}
memory_pll_init(0,NULL);
//serial_put_dword(get_timer(0));
//serial_put_dword(readl(0xc1100000+0x200b*4));
#if CONFIG_ENABLE_SPL_DEBUG_ROM
__udelay(100000);//wait for a uart input
if(serial_tstc()){
writel(0,P_WATCHDOG_TC);//disable Watchdog
debug_rom(__FILE__,__LINE__);
}
#else
__udelay(1000);//delay 1 ms , wait pll ready
#endif
#if 1
#if CONFIG_ENABLE_SPL_DEBUG_ROM
if(ddr_init_test()){
writel(0,P_WATCHDOG_TC);//disable Watchdog
debug_rom(__FILE__,__LINE__);
}
#else
do{
}while(ddr_init_test(0x6));
#endif
#endif
writel(0,P_WATCHDOG_TC);//disable Watchdog
//serial_puts("\nM2C (Haier TV) Systemp Started\n");
}
s32 pwrap_init(void)
{
s32 sub_return = 0;
s32 sub_return1 = 0;
u16 rdata = 0x0;
setbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);
/* add 1us delay for toggling SW reset */
udelay(1);
/* clear reset bit */
clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);
/* Enable DCM */
write32(&mtk_pwrap->dcm_en, 3);
write32(&mtk_pwrap->dcm_dbc_prd, 0);
/* Reset SPISLV */
sub_return = pwrap_reset_spislv();
if (sub_return != 0) {
pwrap_err("error,pwrap_reset_spislv fail,sub_return=%#x\n",
sub_return);
return E_PWR_INIT_RESET_SPI;
}
/* Enable WACS2 */
write32(&mtk_pwrap->wrap_en, 1);
write32(&mtk_pwrap->hiprio_arb_en, WACS2);
write32(&mtk_pwrap->wacs2_en, 1);
/* SIDLY setting */
sub_return = pwrap_init_sidly();
if (sub_return != 0) {
pwrap_err("error,pwrap_init_sidly fail,sub_return=%#x\n",
sub_return);
return E_PWR_INIT_SIDLY;
}
/*
* SPI Waveform Configuration
* 18MHz/26MHz/safe mode/
*/
sub_return = pwrap_init_reg_clock(REG_CLOCK_26MHZ);
if (sub_return != 0) {
pwrap_err("error,pwrap_init_reg_clock fail,sub_return=%#x\n",
sub_return);
return E_PWR_INIT_REG_CLOCK;
}
/*
* Enable PMIC
*/
pwrap_read_nochk(PMIC_WRP_CKPDN, &rdata);
sub_return = pwrap_write_nochk(PMIC_WRP_CKPDN, rdata & 0x50);
/* clear dewrap reset bit */
sub_return1 = pwrap_write_nochk(PMIC_WRP_RST_CON, 0);
if ((sub_return != 0) || (sub_return1 != 0)) {
pwrap_err("Enable PMIC fail, sub_return=%#x sub_return1=%#x\n",
sub_return, sub_return1);
return E_PWR_INIT_ENABLE_PMIC;
}
/* Enable DIO mode */
sub_return = pwrap_init_dio(1);
if (sub_return != 0) {
pwrap_err("pwrap_init_dio error code=%#x, sub_return=%#x\n",
0x11, sub_return);
return E_PWR_INIT_DIO;
}
/*
* Write test using WACS2,
* make sure the read/write function ready
*/
sub_return = pwrap_write_nochk(DEW_WRITE_TEST, WRITE_TEST_VALUE);
sub_return1 = pwrap_read_nochk(DEW_WRITE_TEST, &rdata);
if ((rdata != WRITE_TEST_VALUE) || (sub_return != 0)
|| (sub_return1 != 0)) {
pwrap_err("write error, rdata=%#x, return=%#x, return1=%#x\n",
rdata, sub_return, sub_return1);
return E_PWR_INIT_WRITE_TEST;
}
/* Signature Checking - Using CRC
* should be the last to modify WRITE_TEST
*/
sub_return = pwrap_write_nochk(DEW_CRC_EN, 0x1);
if (sub_return != 0) {
pwrap_err("enable CRC fail,sub_return=%#x\n", sub_return);
return E_PWR_INIT_ENABLE_CRC;
}
write32(&mtk_pwrap->crc_en, 0x1);
write32(&mtk_pwrap->sig_mode, 0x0);
write32(&mtk_pwrap->sig_adr, DEW_CRC_VAL);
/* PMIC_WRAP enables */
write32(&mtk_pwrap->hiprio_arb_en, 0x1ff);
write32(&mtk_pwrap->wacs0_en, 0x1);
write32(&mtk_pwrap->wacs1_en, 0x1);
/*
* switch event pin from usbdl mode to normal mode for pmic interrupt,
* NEW@MT6397
*/
pwrap_read_nochk(PMIC_TOP_CKCON3, &rdata);
sub_return = pwrap_write_nochk(PMIC_TOP_CKCON3, (rdata & 0x0007));
if (sub_return != 0)
pwrap_err("!!switch event pin fail,sub_return=%d\n",
sub_return);
/* Initialization Done */
write32(&mtk_pwrap->init_done2, 0x1);
write32(&mtk_pwrap->init_done0, 0x1);
write32(&mtk_pwrap->init_done1, 0x1);
return 0;
}
/*
* flushes the i2stx fifo
*
* @param i2s_reg i2s regiter address
* @param flush Tx fifo flush command (0x00 - do not flush
* 0x80 - flush tx fifo)
*/
void i2s_fifo(struct exynos5_i2s *i2s_reg, unsigned int flush)
{
/* Flush the FIFO */
setbits_le32(&i2s_reg->fic, flush);
clrbits_le32(&i2s_reg->fic, flush);
}
/* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */
void usb_setup_utmip(void *usb_base)
{
struct usb_ctlr *usb = (struct usb_ctlr *)usb_base;
/* KHz formulas were guessed from U-Boot constants. Formats unclear. */
int khz = clock_get_pll_input_khz();
/* Stop UTMI+ crystal clock while we mess with its settings */
clrbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */
udelay(1);
/* Take stuff out of pwrdn and add some magic numbers from U-Boot */
write32(0x8 << 25 | /* HS slew rate [10:4] */
0x3 << 22 | /* HS driver output 'SETUP' [6:4] */
0 << 21 | /* LS bias selection */
0 << 18 | /* PDZI pwrdn */
0 << 16 | /* PD2 pwrdn */
0 << 14 | /* PD pwrdn */
1 << 13 | /* (rst) HS receiver terminations */
0x1 << 10 | /* (rst) LS falling slew rate */
0x1 << 8 | /* (rst) LS rising slew rate */
0x4 << 0 | /* HS driver output 'SETUP' [3:0] */
0, &usb->utmip.xcvr0);
write32(0x7 << 18 | /* Termination range adjustment */
0 << 4 | /* PDDR pwrdn */
0 << 2 | /* PDCHRP pwrdn */
0 << 0 | /* PDDISC pwrdn */
0, &usb->utmip.xcvr1);
write32(1 << 19 | /* FS send initial J before sync(?) */
1 << 16 | /* (rst) Allow stuff error on SoP */
1 << 9 | /* (rst) Check disc only on EoP */
0, &usb->utmip.tx);
write32(0x2 << 30 | /* (rst) Keep pattern on active */
1 << 28 | /* (rst) Realign inertia on pkt */
0x1 << 24 | /* (rst) edges-1 to move sampling */
0x3 << 21 | /* (rst) squelch delay on EoP */
0x11 << 15 | /* cycles until IDLE */
0x10 << 10 | /* elastic input depth */
0, &usb->utmip.hsrx0);
/* U-Boot claims the USBD values for these are used across all UTMI+
* PHYs. That sounds so horribly wrong that I'm not going to implement
* it, but keep it in mind if we're ever not using the USBD port. */
write32(0x1 << 24 | /* HS disconnect detect level [2] */
1 << 23 | /* (rst) IDPD value */
1 << 22 | /* (rst) IDPD select */
1 << 11 | /* (rst) OTG pwrdn */
0 << 10 | /* bias pwrdn */
0x1 << 2 | /* HS disconnect detect level [1:0] */
0x2 << 0 | /* HS squelch detect level */
0, &usb->utmip.bias0);
write32(khz / 2200 << 3 | /* bias pwrdn cycles (20us?) */
1 << 2 | /* (rst) VBUS wakeup pwrdn */
0 << 0 | /* PDTRK pwrdn */
0, &usb->utmip.bias1);
write32(0xffff << 16 | /* (rst) */
25 * khz / 10 << 0 | /* TODO: what's this, really? */
0, &usb->utmip.debounce);
udelay(1);
setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */
write32(1 << 12 | /* UTMI+ enable */
0 << 11 | /* UTMI+ reset */
0, &usb->suspend_ctrl);
usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
printk(BIOS_DEBUG, "USB controller @ %p set up with UTMI+ PHY\n",usb_base);
}
//POWER key
inline void key_init(void)
{
clrbits_le32(P_RTC_ADDR0, (1<<11));
clrbits_le32(P_RTC_ADDR1, (1<<3));
}
/******************************************************************************
* prcm_init() - inits clocks for PRCM as defined in clocks.h
* called from SRAM, or Flash (using temp SRAM stack).
*****************************************************************************/
void prcm_init(void)
{
u32 osc_clk = 0, sys_clkin_sel;
u32 clk_index, sil_index = 0;
struct prm *prm_base = (struct prm *)PRM_BASE;
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/*
* Gauge the input clock speed and find out the sys_clkin_sel
* value corresponding to the input clock.
*/
osc_clk = get_osc_clk_speed();
get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
/* set input crystal speed */
clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
/* If the input clock is greater than 19.2M always divide/2 */
if (sys_clkin_sel > 2) {
/* input clock divider */
clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
clk_index = sys_clkin_sel / 2;
} else {
/* input clock divider */
clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
clk_index = sys_clkin_sel;
}
if (get_cpu_family() == CPU_OMAP36XX) {
/*
* In warm reset conditions on OMAP36xx/AM/DM37xx
* the rom code incorrectly sets the DPLL4 clock
* input divider to /6.5. Section 3.5.3.3.3.2.1 of
* the AM/DM37x TRM explains that the /6.5 divider
* is used only when the input clock is 13MHz.
*
* If the part is in this cpu family *and* the input
* clock *is not* 13 MHz, then reset the DPLL4 clock
* input divider to /1 as it should never set to /6.5
* in this case.
*/
if (sys_clkin_sel != 1) { /* 13 MHz */
/* Bit 8: DPLL4_CLKINP_DIV */
clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
}
/* Unlock MPU DPLL (slows things down, and needed later) */
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
dpll3_init_36xx(0, clk_index);
dpll4_init_36xx(0, clk_index);
dpll5_init_36xx(0, clk_index);
iva_init_36xx(0, clk_index);
mpu_init_36xx(0, clk_index);
/* Lock MPU DPLL to set frequency */
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
} else {
/*
* The DPLL tables are defined according to sysclk value and
* silicon revision. The clk_index value will be used to get
* the values for that input sysclk from the DPLL param table
* and sil_index will get the values for that SysClk for the
* appropriate silicon rev.
*/
if (((get_cpu_family() == CPU_OMAP34XX)
&& (get_cpu_rev() >= CPU_3XX_ES20)) ||
(get_cpu_family() == CPU_AM35XX))
sil_index = 1;
/* Unlock MPU DPLL (slows things down, and needed later) */
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
dpll3_init_34xx(sil_index, clk_index);
dpll4_init_34xx(sil_index, clk_index);
dpll5_init_34xx(sil_index, clk_index);
if (get_cpu_family() != CPU_AM35XX)
iva_init_34xx(sil_index, clk_index);
mpu_init_34xx(sil_index, clk_index);
/* Lock MPU DPLL to set frequency */
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
}
/* Set up GPTimers to sys_clk source only */
setbits_le32(&prcm_base->clksel_per, 0x000000FF);
setbits_le32(&prcm_base->clksel_wkup, 1);
sdelay(5000);
}
static void rk_edp_enable_sw_function(struct rk_edp *edp)
{
clrbits_le32(&edp->regs->func_en_1, SW_FUNC_EN_N);
}
static void _spi_cs_deactivate(struct kwspi_registers *reg)
{
clrbits_le32(®->ctrl, KWSPI_CSN_ACT);
}
static inline void disable_sdio(unsigned por_config)
{
// //enable power
/* (*P_PREG_JTAG_GPIO_ADDR)&= ~((1<<20) // test_n_gpio_o
|(1<<16)); // test_n_gpio_en_n*/
clrbits_le32(P_PREG_JTAG_GPIO_ADDR,
(1<<16));
switch(POR_GET_SDIO_CFG(por_config))
{
case POR_SDIO_A_ENABLE://SDIOA,GPIOX_31~GPIOX_36
clrbits_le32(P_PERIPHS_PIN_MUX_0,0x3f<<23);
clrbits_le32(P_PREG_EGPIO_EN_N,(0x3f<<13));
clrbits_le32(P_PREG_EGPIO_O,(0x3f<<13));
break;
case POR_SDIO_B_ENABLE://SDIOB,GPIOX_37~GPIOX_42
clrbits_le32(P_PERIPHS_PIN_MUX_1,0x3f);
clrbits_le32(P_PREG_EGPIO_EN_N,(0x3f<<4));
clrbits_le32(P_PREG_EGPIO_O,(0x3f<<4));
break;
case POR_SDIO_C_ENABLE:
clrbits_le32(P_PERIPHS_PIN_MUX_2,(0xf<<16)|(1<<12)|(1<<8));//(0x3f<<21)
clrbits_le32(P_PREG_EGPIO_EN_N,(0x3f<<21));
clrbits_le32(P_PREG_EGPIO_O,(0x3f<<21));
break;
default://SDIOC, GPIOX_17~GPIOX_22, iNAND or eMMC, don't need to send CARD_EN
// disable SPI and SDIO_B
clrbits_le32(P_PERIPHS_PIN_MUX_7,(0x3f<<24));
break;
}
setbits_le32(P_PREG_JTAG_GPIO_ADDR,
(1<<20));
}
static void mxs_enable_4p2_dcdc_input(int xfer)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
uint32_t prev_5v_brnout, prev_5v_droop;
prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_PWDN_5VBRNOUT;
prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
POWER_CTRL_ENIRQ_VDD5V_DROOP;
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
if (xfer && (readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_ENABLE_DCDC)) {
return;
}
/*
* Recording orignal values that will be modified temporarlily
* to handle a chip bug. See chip errata for CQ ENGR00115837
*/
tmp = readl(&power_regs->hw_power_5vctrl);
vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
/*
* Disable mechanisms that get erroneously tripped by when setting
* the DCDC4P2 EN_DCDC
*/
clrbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_5VDETECT |
POWER_5VCTRL_VBUSVALID_TRSH_MASK);
writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
if (xfer) {
setbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_DCDC_XFER);
early_delay(20);
clrbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_DCDC_XFER);
setbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_ENABLE_DCDC);
} else {
setbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_ENABLE_DCDC);
}
early_delay(25);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
if (vbus_5vdetect)
writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
if (!pwd_bo)
clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
writel(POWER_CTRL_VBUS_VALID_IRQ,
&power_regs->hw_power_ctrl_clr);
if (prev_5v_brnout) {
writel(POWER_5VCTRL_PWDN_5VBRNOUT,
&power_regs->hw_power_5vctrl_set);
writel(POWER_RESET_UNLOCK_KEY,
&power_regs->hw_power_reset);
} else {
writel(POWER_5VCTRL_PWDN_5VBRNOUT,
&power_regs->hw_power_5vctrl_clr);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
}
while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
writel(POWER_CTRL_VDD5V_DROOP_IRQ,
&power_regs->hw_power_ctrl_clr);
if (prev_5v_droop)
clrbits_le32(&power_regs->hw_power_ctrl,
POWER_CTRL_ENIRQ_VDD5V_DROOP);
else
setbits_le32(&power_regs->hw_power_ctrl,
POWER_CTRL_ENIRQ_VDD5V_DROOP);
}
/**
* mxs_power_enable_4p2() - Power up the 4P2 regulator
*
* This function drives the process of powering up the 4P2 linear regulator
* and switching the DC-DC converter input over to the 4P2 linear regulator.
*/
static void mxs_power_enable_4p2(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t vdddctrl, vddactrl, vddioctrl;
uint32_t tmp;
debug("SPL: Powering up 4P2 regulator\n");
vdddctrl = readl(&power_regs->hw_power_vdddctrl);
vddactrl = readl(&power_regs->hw_power_vddactrl);
vddioctrl = readl(&power_regs->hw_power_vddioctrl);
setbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
POWER_VDDDCTRL_PWDN_BRNOUT);
setbits_le32(&power_regs->hw_power_vddactrl,
POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
POWER_VDDACTRL_PWDN_BRNOUT);
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
mxs_power_init_4p2_params();
mxs_power_init_4p2_regulator();
/* Shutdown battery (none present) */
if (!mxs_is_batt_ready()) {
clrbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK);
writel(POWER_CTRL_DCDC4P2_BO_IRQ,
&power_regs->hw_power_ctrl_clr);
writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
&power_regs->hw_power_ctrl_clr);
}
mxs_power_init_dcdc_4p2_source();
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
early_delay(20);
writel(vddactrl, &power_regs->hw_power_vddactrl);
early_delay(20);
writel(vddioctrl, &power_regs->hw_power_vddioctrl);
/*
* Check if FET is enabled on either powerout and if so,
* disable load.
*/
tmp = 0;
tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
POWER_VDDDCTRL_DISABLE_FET);
tmp |= !(readl(&power_regs->hw_power_vddactrl) &
POWER_VDDACTRL_DISABLE_FET);
tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
POWER_VDDIOCTRL_DISABLE_FET);
if (tmp)
writel(POWER_CHARGE_ENABLE_LOAD,
&power_regs->hw_power_charge_clr);
debug("SPL: 4P2 regulator powered-up\n");
}
static int pch_power_options(const void *blob, int node, pci_dev_t dev)
{
u8 reg8;
u16 reg16, pmbase;
u32 reg32;
const char *state;
int pwr_on;
int nmi_option;
int ret;
/*
* Which state do we want to goto after g3 (power restored)?
* 0 == S0 Full On
* 1 == S5 Soft Off
*
* If the option is not existent (Laptops), use Kconfig setting.
* TODO([email protected]): Make this configurable
*/
pwr_on = MAINBOARD_POWER_ON;
reg16 = x86_pci_read_config16(dev, GEN_PMCON_3);
reg16 &= 0xfffe;
switch (pwr_on) {
case MAINBOARD_POWER_OFF:
reg16 |= 1;
state = "off";
break;
case MAINBOARD_POWER_ON:
reg16 &= ~1;
state = "on";
break;
case MAINBOARD_POWER_KEEP:
reg16 &= ~1;
state = "state keep";
break;
default:
state = "undefined";
}
reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
reg16 &= ~(1 << 10);
reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
x86_pci_write_config16(dev, GEN_PMCON_3, reg16);
debug("Set power %s after power failure.\n", state);
/* Set up NMI on errors. */
reg8 = inb(0x61);
reg8 &= 0x0f; /* Higher Nibble must be 0 */
reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
reg8 |= (1 << 2); /* PCI SERR# Disable for now */
outb(reg8, 0x61);
reg8 = inb(0x70);
/* TODO([email protected]): Make this configurable */
nmi_option = NMI_OFF;
if (nmi_option) {
debug("NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */
} else {
debug("NMI sources disabled.\n");
/* Can't mask NMI from PCI-E and NMI_NOW */
reg8 |= (1 << 7);
}
outb(reg8, 0x70);
/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
#if DEBUG_PERIODIC_SMIS
/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
reg16 |= (3 << 0); /* Periodic SMI every 8s */
#endif
x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
/* Set the board's GPI routing. */
ret = pch_gpi_routing(blob, node, dev);
if (ret)
return ret;
pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe;
writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
"intel,gpe0-enable", 0));
writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
"intel,alt-gp-smi-enable", 0));
/* Set up power management block and determine sleep mode */
reg32 = inl(pmbase + 0x04); /* PM1_CNT */
reg32 &= ~(7 << 10); /* SLP_TYP */
reg32 |= (1 << 0); /* SCI_EN */
outl(reg32, pmbase + 0x04);
/* Clear magic status bits to prevent unexpected wake */
setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
clrbits_le32(RCB_REG(0x3f02), 0xf);
return 0;
}
static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
{
u32 reg;
/* enabling usb_drd phy */
set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
/* Reset USB 3.0 PHY */
writel(0x0, &phy->phy_reg0);
clrbits_le32(&phy->phy_param0,
/* Select PHY CLK source */
PHYPARAM0_REF_USE_PAD |
/* Set Loss-of-Signal Detector sensitivity */
PHYPARAM0_REF_LOSLEVEL_MASK);
setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
writel(0x0, &phy->phy_resume);
/*
* Setting the Frame length Adj value[6:1] to default 0x20
* See xHCI 1.0 spec, 5.2.4
*/
setbits_le32(&phy->link_system,
LINKSYSTEM_XHCI_VERSION_CONTROL |
LINKSYSTEM_FLADJ(0x20));
/* Set Tx De-Emphasis level */
clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
/* PHYTEST POWERDOWN Control */
clrbits_le32(&phy->phy_test,
PHYTEST_POWERDOWN_SSP |
PHYTEST_POWERDOWN_HSP);
/* UTMI Power Control */
writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
/* Use core clock from main PLL */
reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
/* Default 24Mhz crystal clock */
PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
PHYCLKRST_SSC_REFCLKSEL(0x88) |
/* Force PortReset of PHY */
PHYCLKRST_PORTRESET |
/* Digital power supply in normal operating mode */
PHYCLKRST_RETENABLEN |
/* Enable ref clock for SS function */
PHYCLKRST_REF_SSP_EN |
/* Enable spread spectrum */
PHYCLKRST_SSC_EN |
/* Power down HS Bias and PLL blocks in suspend mode */
PHYCLKRST_COMMONONN;
writel(reg, &phy->phy_clk_rst);
/* giving time to Phy clock to settle before resetting */
udelay(10);
reg &= ~PHYCLKRST_PORTRESET;
writel(reg, &phy->phy_clk_rst);
}
void enter_power_down()
{
int i;
unsigned v1,v2,v;
unsigned rtc_ctrl;
unsigned power_key;
//*******************************************
//* power down flow
//*******************************************
f_serial_puts("\n");
wait_uart_empty();
// disable jtag
setbits_le32(P_AO_RTI_PIN_MUX_REG, 1<<13);
clrbits_le32(P_AO_RTI_PIN_MUX_REG, 1<<14);
// turn off mali clock
clrbits_le32(P_HHI_MALI_CLK_CNTL, 1 << 8);
// disable all memory accesses.
disable_mmc_req();
//save registers for clk and ddr
store_restore_plls(1);
//mmc enter sleep
mmc_sleep();
// delay_ms(20);
// save ddr power
APB_Wr(MMC_PHY_CTRL, APB_Rd(MMC_PHY_CTRL)|(1<<0)|(1<<8)|(1<<13));
APB_Wr(PCTL_PHYCR_ADDR, APB_Rd(PCTL_PHYCR_ADDR)|(1<<6));
APB_Wr(PCTL_DLLCR9_ADDR, APB_Rd(PCTL_DLLCR9_ADDR)|(1<<31));
// delay_ms(20);
// power down DDR
writel(readl(P_HHI_DDR_PLL_CNTL)|(1<<15),P_HHI_DDR_PLL_CNTL);
// enable retention
enable_retention();
writel(0,P_AO_RTI_STATUS_REG1);
// reset A9
// setbits_le32(P_A9_CFG2, 7<<16);
clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL, 1<<4); // disable APB_CLK
clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL, 1<<5); // disable AT_CLK
setbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19);
udelay(10);
// enable iso ee for A9
writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<4)),P_AO_RTI_PWR_CNTL_REG0);
udelay(1000);
#ifdef POWER_OFF_HDMI_VCC
reg7_off();
#endif
#ifdef POWER_OFF_AVDD33
reg5_off();
#endif
#ifdef POWER_OFF_EE
//iso EE from AO
//comment isolate EE. otherwise cannot detect power key.
// writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<0)),P_AO_RTI_PWR_CNTL_REG0);
writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<2)),P_AO_RTI_PWR_CNTL_REG0);
writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<3)),P_AO_RTI_PWR_CNTL_REG0);
//?? Gate off clk81 to EE domain
writel(readl(P_AO_RTI_GEN_CNTL_REG0)&(~(1<<12)),P_AO_RTI_GEN_CNTL_REG0);
//-------------------------------
//turn off EE voltage
//v = readl(0xC8100024);
//v &= ~(1<<9);
//v &= ~(1<<25);
//writel(v,0xC8100024);
#else
// ee use 32k
writel(readl(P_HHI_MPEG_CLK_CNTL)|(1<<9),P_HHI_MPEG_CLK_CNTL);
#endif
// change RTC filter for 32k
rtc_ctrl = readl(0xC810074c);
//writel(0x00800000,0xC810074c);
writel(0,0xC810074c);
// switch to 32k
writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(1<<8),P_AO_RTI_PWR_CNTL_REG0);
udelay(100);
#ifdef POWER_OFF_VDDIO
vddio_off();
#endif
#ifdef POWER_OFF_AVDD25
reg6_off();
#endif
#ifdef POWER_OFF_VCC
power_off_VCC(0);
#endif
udelay(100);
#if (defined(POWER_DOWN_VCC12) || defined(POWER_DOWN_DDR))
switch_voltage(1);
#endif
#ifdef POWER_DOWN_DDR
powerdown_ddr();
#endif
#ifdef POWER_DOWN_VCC12
powerdown_vcc12();
#endif
// gate off REMOTE, UART
//writel(readl(P_AO_RTI_GEN_CNTL_REG0)&(~(0xF)),P_AO_RTI_GEN_CNTL_REG0);
// wait key
#if 1
//backup the remote config (on arm)
backup_remote_register();
//set the ir_remote to 32k mode at ARC
init_custom_trigger();
//set the detect gpio
//setbits_le32(P_AO_GPIO_O_EN_N,(1<<3));
while(1)
{
//detect remote key
power_key=readl(P_AO_IR_DEC_FRAME);
if(power_key==0xf50a7748) break;
//detect IO key
/*power_key=readl(P_AO_GPIO_I);
power_key=power_key&(1<<3);
if(!power_key)
break;
*/
#ifdef RTC_AUTO_WAKE_UP
power_key = readl(0xc8100744);
if((power_key&8) != 0) break;
#endif
}
#elif 1
power_key = readl(0Xc8100744);
while (((power_key&4) != 0)&&((power_key&8) == 0))
{
power_key = readl(0Xc8100744);
}
#else
for(i=0;i<64;i++)
{
udelay(1000);
//udelay(1000);
}
#endif
// gate on REMOTE, I2C s/m, UART
//writel(readl(P_AO_RTI_GEN_CNTL_REG0)|0xF, P_AO_RTI_GEN_CNTL_REG0);
udelay(10);
#ifdef POWER_DOWN_DDR
powerup_ddr();
#endif
#ifdef POWER_DOWN_VCC12
powerup_vcc12();
#endif
#if (defined(POWER_DOWN_VCC12) || defined(POWER_DOWN_DDR))
switch_voltage(0);
#endif
#ifdef POWER_OFF_VCC
power_off_VCC(1);
#endif
#ifdef POWER_OFF_AVDD25
reg6_on();
#endif
#ifdef POWER_OFF_VDDIO
vddio_on();
#endif
udelay(100);
// switch to clk81
writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(0x1<<8)),P_AO_RTI_PWR_CNTL_REG0);
udelay(100);
// restore RTC filter
writel(rtc_ctrl,0xC810074c);
// set AO interrupt mask
writel(0xFFFF,P_AO_IRQ_STAT_CLR);
#ifdef POWER_OFF_EE
//turn on EE voltage
//v = readl(0xC8100024);
//v &= ~(1<<9);
//v |= (1<<25);
//writel(v,0xC8100024);
//delay_ms(200);
// un-iso AO domain from EE bit0=signals, bit1=reset, bit2=irq, bit3=test_mode
writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(0xD<<0),P_AO_RTI_PWR_CNTL_REG0);
//un isolate the reset in the EE
writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(0x1<<5),P_AO_RTI_PWR_CNTL_REG0);
writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(0x1<<5)|(1<<3)|(1<<2)|(1<<1)|(1<<0), \
P_AO_RTI_PWR_CNTL_REG0);
#else
// ee go back to clk81
writel(readl(P_HHI_MPEG_CLK_CNTL)&(~(0x1<<9)),P_HHI_MPEG_CLK_CNTL);
#endif
#ifdef POWER_OFF_AVDD33
reg5_on();
#endif
#ifdef POWER_OFF_HDMI_VCC
reg7_on();
#endif
store_restore_plls(0);
init_ddr_pll();
udelay(1000);
uart_reset();
reset_mmc();
// initialize mmc and put it to sleep
init_pctl();
mmc_sleep();
// disable retention
disable_retention();
// Next, we wake up
mmc_wakeup();
// Next, we enable all requests
enable_mmc_req();
// f_serial_puts("restart arm...\n");
//0. make sure a9 reset
setbits_le32(P_A9_CFG2,1<<17); // release APB reset
udelay(1000);
setbits_le32(P_A9_CFG2,1<<16); // release AXI reset
udelay(1000);
setbits_le32(P_A9_CFG2,1<<18); // release A9DBG reset
udelay(1000);
setbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19);
udelay(1000);
//1. write flag
if (power_key&8)
writel(0xabcd1234,P_AO_RTI_STATUS_REG2);
else
writel(0x1234abcd,P_AO_RTI_STATUS_REG2);
//2. remap AHB SRAM
writel(3,P_AO_REMAP_REG0);
writel(2,P_AHB_ARBDEC_REG);
//3. turn off romboot clock
writel(readl(P_HHI_GCLK_MPEG1)&0x7fffffff,P_HHI_GCLK_MPEG1);
//4. Release ISO for A9 domain.
setbits_le32(P_AO_RTI_PWR_CNTL_REG0,1<<4);
udelay(1000);
writel( (0 << 9) | // select xtal as clock source
(0 << 0) ,
P_HHI_MALI_CLK_CNTL);
delay_ms(1);
setbits_le32(P_HHI_SYS_CPU_CLK_CNTL, (1<<14)|(1<<15)); // soft reset
udelay(10);
clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL, (1<<14)|(1<<15)); // soft reset
udelay(1000);
//reset A9
writel(0xF,P_RESET4_REGISTER);// -- reset arm.ww
writel(1<<14,P_RESET2_REGISTER);// -- reset arm.mali
udelay(1000);
clrbits_le32(P_A9_CFG2,1<<17); // release APB reset
udelay(1000);
clrbits_le32(P_A9_CFG2,1<<16); // release AXI reset
udelay(1000);
clrbits_le32(P_A9_CFG2,1<<18); // release A9DBG reset
udelay(1000);
setbits_le32(P_HHI_SYS_CPU_CLK_CNTL, 1<<4); // enable APB_CLK
udelay(10);
clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19); // release A9 reset
udelay(1000);
//reset the IR REMOTE
resume_remote_register();
// delay_1s();
// delay_1s();
// delay_1s();
}
static inline void mu_hal_init(struct mu_type *base)
{
/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK |
MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK);
}
void dramc_sw_impedance(const struct sdram_params *params)
{
u8 term = 0, ca_term = ODT_OFF, dq_term = ODT_ON;
u32 sw_impedance[2][4] = {0};
for (term = 0; term < 2; term++)
for (u8 i = 0; i < 4; i++)
sw_impedance[term][i] = params->impedance[term][i];
sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2];
sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3];
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3);
sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP);
/* DQ */
clrsetbits_le32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0),
(sw_impedance[dq_term][0] << 5) |
(sw_impedance[dq_term][1] << 0));
clrsetbits_le32(&ch[0].ao.shu[0].drving[1],
(0x1f << 25)|(0x1f << 20) | (1 << 31),
(sw_impedance[dq_term][0] << 25) |
(sw_impedance[dq_term][1] << 20) | (!dq_term << 31));
clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0),
(sw_impedance[dq_term][2] << 5) |
(sw_impedance[dq_term][3] << 0));
clrsetbits_le32(&ch[0].ao.shu[0].drving[3], (0x1f << 25) | (0x1f << 20),
(sw_impedance[dq_term][2] << 25) |
(sw_impedance[dq_term][3] << 20));
/* DQS */
for (u8 i = 0; i <= 2; i += 2) {
clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
(0x1f << 25) | (0x1f << 20),
(sw_impedance[dq_term][i] << 25) |
(sw_impedance[dq_term][i + 1] << 20));
clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
(0x1f << 15) | (0x1f << 10),
(sw_impedance[dq_term][i] << 15) |
(sw_impedance[dq_term][i + 1] << 10));
}
/* CMD & CLK */
for (u8 i = 1; i <= 3; i += 2) {
clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
(0x1f << 15) | (0x1f << 10),
(sw_impedance[ca_term][i - 1] << 15) |
(sw_impedance[ca_term][i] << 10));
clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
(0x1f << 5) | (0x1f << 0),
(sw_impedance[ca_term][i - 1] << 5) |
(sw_impedance[ca_term][i] << 0));
}
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 17,
sw_impedance[ca_term][0] << 17);
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22,
sw_impedance[ca_term][1] << 22);
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[3],
SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_MASK,
1 << SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_SHIFT);
clrbits_le32(&ch[0].phy.shu[0].ca_cmd[0],
SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_MASK);
clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16);
}
int enter_boot_power_down()
{
int key;
int ac;
power_gate_init();
lcd_disable();
video_dac_disable();
camera_power_off() ;
vcc2_power_off();
//turn_off_audio_DAC();
if (!early_suspend_flag) {
printf("\n boot_suspend \n");
// if (pdata->set_exgpio_early_suspend) {
// pdata->set_exgpio_early_suspend(OFF);
// }
early_power_gate_switch(OFF);
early_clk_switch(OFF);
early_pll_switch(OFF);
early_suspend_flag = 1;
}
printf("enter boot_pm_suspend!\n");
analog_switch(OFF);
usb_switch(OFF, 0);
usb_switch(OFF, 1);
// if (pdata->set_vccx2) {
// pdata->set_vccx2(OFF);
// }
power_gate_switch(OFF);
clk_switch(OFF);
pll_switch(OFF);
clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<7); //change A9-->24M
printf("boot sleep ...\n");
// WRITE_MPEG_REG_BITS(HHI_MALI_CLK_CNTL, 0, 9, 3); // mali use xtal
// CLEAR_CBUS_REG_MASK(HHI_SYS_CPU_CLK_CNTL, 1<<7); // a9 use xtal
// SET_CBUS_REG_MASK(HHI_SYS_PLL_CNTL, (1 << 15)); // turn off sys pll
//
// meson_power_suspend();
key = powerkey_scan();
ac = axp_charger_is_ac_online();
while((!key)&&ac)
{
key = powerkey_scan();
ac = axp_charger_is_ac_online();
}
setbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<7); //change A9-->normal
printf("boot... wake up\n");
// if (pdata->set_vccx2) {
// pdata->set_vccx2(ON);
// }
SET_CBUS_REG_MASK(HHI_SYS_CPU_CLK_CNTL, (1 << 7)); // a9 use pll
WRITE_MPEG_REG_BITS(HHI_MALI_CLK_CNTL, 3, 9, 3); // mali use pll
pll_switch(ON);
clk_switch(ON);
power_gate_switch(ON);
usb_switch(ON, 0);
usb_switch(ON, 1);
analog_switch(ON);
if (early_suspend_flag) {
early_pll_switch(ON);
early_clk_switch(ON);
early_power_gate_switch(ON);
early_suspend_flag = 0;
printf("boot sys_resume\n");
}
printf("mlvds init\n");
lcd_enable();
printf("mlvds init finish\n");
return ac;
}
void clock_gate(void)
{
/* CLK_GATE_IP_SYSRGT */
clrbits_le32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK);
/* CLK_GATE_IP_ACP */
clrbits_le32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK |
CLK_SMMUSSS_MASK |
CLK_SMMUMDMA_MASK |
CLK_ID_REMAPPER_MASK |
CLK_G2D_MASK |
CLK_SSS_MASK |
CLK_MDMA_MASK |
CLK_SECJTAG_MASK);
/* CLK_GATE_BUS_SYSLFT */
clrbits_le32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK);
/* CLK_GATE_IP_ISP0 */
clrbits_le32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK |
CLK_WDT_ISP_MASK |
CLK_PWM_ISP_MASK |
CLK_MTCADC_ISP_MASK |
CLK_I2C1_ISP_MASK |
CLK_I2C0_ISP_MASK |
CLK_MPWM_ISP_MASK |
CLK_MCUCTL_ISP_MASK |
CLK_INT_COMB_ISP_MASK |
CLK_SMMU_MCUISP_MASK |
CLK_SMMU_SCALERP_MASK |
CLK_SMMU_SCALERC_MASK |
CLK_SMMU_FD_MASK |
CLK_SMMU_DRC_MASK |
CLK_SMMU_ISP_MASK |
CLK_GICISP_MASK |
CLK_ARM9S_MASK |
CLK_MCUISP_MASK |
CLK_SCALERP_MASK |
CLK_SCALERC_MASK |
CLK_FD_MASK |
CLK_DRC_MASK |
CLK_ISP_MASK);
/* CLK_GATE_IP_ISP1 */
clrbits_le32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK |
CLK_SPI0_ISP_MASK |
CLK_SMMU3DNR_MASK |
CLK_SMMUDIS1_MASK |
CLK_SMMUDIS0_MASK |
CLK_SMMUODC_MASK |
CLK_3DNR_MASK |
CLK_DIS_MASK |
CLK_ODC_MASK);
/* CLK_GATE_SCLK_ISP */
clrbits_le32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK);
/* CLK_GATE_IP_GSCL */
clrbits_le32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK |
CLK_SMMUFIMC_LITE1_MASK |
CLK_SMMUFIMC_LITE0_MASK |
CLK_SMMUGSCL3_MASK |
CLK_SMMUGSCL2_MASK |
CLK_SMMUGSCL1_MASK |
CLK_SMMUGSCL0_MASK |
CLK_GSCL_WRAP_B_MASK |
CLK_GSCL_WRAP_A_MASK |
CLK_CAMIF_TOP_MASK |
CLK_GSCL3_MASK |
CLK_GSCL2_MASK |
CLK_GSCL1_MASK |
CLK_GSCL0_MASK);
/* CLK_GATE_IP_DISP1 */
clrbits_le32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK |
CLK_ASYNCTVX_MASK |
CLK_HDMI_MASK |
CLK_MIXER_MASK |
CLK_DSIM1_MASK);
/* CLK_GATE_IP_MFC */
clrbits_le32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK |
CLK_SMMUMFCL_MASK |
CLK_MFC_MASK);
/* CLK_GATE_IP_GEN */
clrbits_le32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK |
CLK_SMMUJPEG_MASK |
CLK_SMMUROTATOR_MASK |
CLK_MDMA1_MASK |
CLK_JPEG_MASK |
CLK_ROTATOR_MASK);
/* CLK_GATE_IP_FSYS */
clrbits_le32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK |
CLK_SMMUMCU_IOP_MASK |
CLK_SATA_PHY_I2C_MASK |
CLK_SATA_PHY_CTRL_MASK |
CLK_MCUCTL_MASK |
CLK_NFCON_MASK |
CLK_SMMURTIC_MASK |
CLK_RTIC_MASK |
CLK_MIPI_HSI_MASK |
CLK_USBOTG_MASK |
CLK_SATA_MASK |
CLK_PDMA1_MASK |
CLK_PDMA0_MASK |
CLK_MCU_IOP_MASK);
/* CLK_GATE_IP_PERIC */
clrbits_le32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK |
CLK_HS_I2C2_MASK |
CLK_HS_I2C1_MASK |
CLK_HS_I2C0_MASK |
CLK_AC97_MASK |
CLK_SPDIF_MASK |
CLK_PCM2_MASK |
CLK_PCM1_MASK |
CLK_I2S2_MASK |
CLK_SPI2_MASK |
CLK_SPI0_MASK);
/*
* CLK_GATE_IP_PERIS
* Note: Keep CHIPID_APBIF ungated to ensure reading the product ID
* register (PRO_ID) works correctly when the OS kernel determines
* which chip it is running on.
*/
clrbits_le32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK |
CLK_TZPC9_MASK |
CLK_TZPC8_MASK |
CLK_TZPC7_MASK |
CLK_TZPC6_MASK |
CLK_TZPC5_MASK |
CLK_TZPC4_MASK |
CLK_TZPC3_MASK |
CLK_TZPC2_MASK |
CLK_TZPC1_MASK |
CLK_TZPC0_MASK);
/* CLK_GATE_BLOCK */
clrbits_le32(&exynos_clock->gate_block, CLK_ACP_MASK);
/* CLK_GATE_IP_CDREX */
clrbits_le32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK |
CLK_DPHY1_MASK |
CLK_TZASC_DRBXR_MASK);
}
static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
{
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
void (*f_lock_pll) (u32, u32, u32, u32);
int xip_safe, p0, p1, p2, p3;
xip_safe = is_running_in_sram();
/* Moving it to the right sysclk base */
ptr += clk_index;
if (xip_safe) {
/* CORE DPLL */
/* Select relock bypass: CM_CLKEN_PLL[0:2] */
clrsetbits_le32(&prcm_base->clken_pll,
0x00000007, PLL_FAST_RELOCK_BYPASS);
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
LDELAY);
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
clrsetbits_le32(&prcm_base->clksel1_emu,
0x001F0000, CORE_M3X2 << 16);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
clrsetbits_le32(&prcm_base->clksel1_pll,
0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
clrsetbits_le32(&prcm_base->clksel1_pll,
0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
clrsetbits_le32(&prcm_base->clksel1_pll,
0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
/* SSI */
clrsetbits_le32(&prcm_base->clksel_core,
0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
clrsetbits_le32(&prcm_base->clksel_core,
0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
clrsetbits_le32(&prcm_base->clksel_core,
0x0000000C, CORE_L4_DIV << 2);
/* L3 */
clrsetbits_le32(&prcm_base->clksel_core,
0x00000003, CORE_L3_DIV);
/* GFX */
clrsetbits_le32(&prcm_base->clksel_gfx,
0x00000007, GFX_DIV_36X);
/* RESET MGR */
clrsetbits_le32(&prcm_base->clksel_wkup,
0x00000006, WKUP_RSM << 1);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
clrsetbits_le32(&prcm_base->clken_pll,
0x000000F0, ptr->fsel << 4);
/* LOCK MODE */
clrsetbits_le32(&prcm_base->clken_pll,
0x00000007, PLL_LOCK);
wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
LDELAY);
} else if (is_running_in_flash()) {
/*
* if running from flash, jump to small relocated code
* area in SRAM.
*/
f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
p1 = readl(&prcm_base->clksel1_pll);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
clrbits_le32(&p1, 0x00000040);
p2 = readl(&prcm_base->clksel_core);
/* SSI */
clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
p3 = (u32)&prcm_base->idlest_ckgen;
(*f_lock_pll) (p0, p1, p2, p3);
}
}
void exynos_fimd_disable(void)
{
writel(0, &exynos_fimd->wincon0);
clrbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN);
}
void v7_outer_cache_disable(void)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
